A Newly Designed Planar Stacked Capacitor Cell with High dielectric Constant Film for 256Mbit DRAM

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 631-634

  Eimori, T ^a   Ohno, Y ^a   Kimura, H ^a   Matsufusa, J ^a   Kishimura, S ^a   Yoshida, A ^a   Sumitani, H ^a   Maruyama, T ^a   Hayashide, Y ^a   Moriizumi, K ^a   Katayama, T ^a   Asakura, M ^a   Horikawa, T ^a   Shibano, T ^a   Itoh, H ^a   Sato, K ^a   Namba, K ^a   Nishimura, T ^a   Satoh, S ^a   Miyoshi, H ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BARIUM COMPOUNDS; CELLS; CYTOLOGY; DIELECTRIC FILMS; FILM THICKNESS; INTEGRATED CIRCUIT DESIGN; STRONTIUM COMPOUNDS; THIN FILMS; CAPACITORS; CELLULAR ARRAYS; DIELECTRIC MATERIALS; SEMICONDUCTOR DEVICE MANUFACTURE;

BIT LINES; CAPACITOR CELLS; CAPACITOR DIELECTRICS; CELL CAPACITANCE; CELL DESIGN; CELL STRUCTURE; CELL-SIZE; HIGH DIELECTRIC CONSTANTS; PARASITICS CAPACITANCE; THIN-FILMS;

CAPACITANCE; RANDOM ACCESS STORAGE;

BITLINE PARASITIC CAPACITANCE; LITHOGRAPHIC TOLERANCE; PLANAR STACKED CAPACITOR CELL;

EID: 0027850961     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. M. Sakao, N. Kasai, T. Ishijima, E. Ikawa, H. Watanabe, K. Terada and T. Kikkawa,"A Capacitor-Over-Bit-line (COB) Cell with a Hemispherical-grain Storage Node for 64Mb DRAMs," IEDM Tech. Dig., pp655-658, 1990
2. H.Arima, A.Hachisuka, T.Ogawa, Y.Okumura, Y.Matsui, K.Motonami, T.Matsukawa and N.Tsubouchi, "A Novel Stacked Capasitor Cell with Dual Cell Plate for 64Mb DRAMs," EDM Tech. Dig., pp 651-654, 1990
3. Y.Hayashide, H.Miyatake, J.Mitsuhashi, M.Hirayama, T. Higaki and H.Abe,"Fabrication of Storage Capacitance-Enhanced Capacitors with a Rough Electrode," Extended Abst. of 22nd SSDM, pp.869-872,1990
4. 3 for 2S6M DRAM," EDM Tech. Dig., p823-826, 1991
5. 2 Leakage Current," IEDM Tech. Dig., p267-7270, 1992