Automated Pin Grid Array Package Routing on Multilayer Ceramic Substrates

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 1, Issue 4, 1993, Pages 571-575

  Ying, Changsheng ^a   Gu, Jun ^a  

^a UNIVERSITY OF CALGARY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CERAMIC MATERIALS; COMPUTER AIDED DESIGN; CONSTRAINT THEORY; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; SUBSTRATES; ULSI CIRCUITS; VLSI CIRCUITS;

AUTOMATED PIN GRID ARRAY PACKAGE ROUTING; GEOMETRICAL CONSTRAINTS; LAYERING AND ROUTING ALGORITHMS; MULTILAYER CERAMIC SUBSTRATES; PACKAGING ROUTING SYSTEM; PIN TO BOUNDARY PATH; PIN TO PAD PATH;

ELECTRONICS PACKAGING;

EID: 0027850771     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.250206     Document Type: Article

References (6)

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