Logic-level model for α-particle hits in CMOS circuits

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1993, Pages 538-542

  Cha, Hungse ^a   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALPHA PARTICLES; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ELECTRIC WAVEFORMS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LOGIC GATES; MATHEMATICAL MODELS; SYSTEMS ANALYSIS; WAVEFORM ANALYSIS;

ALPHA PARTICLE HITS; GATE LEVEL SIMULATORS; LOGIC PULSE WAVEFORM; SOFTWARE PACKAGE SPICE;

CMOS INTEGRATED CIRCUITS;

EID: 0027848063     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)