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1
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0024883413
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Algorithm transformation techniques for concurrent processors
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Dec.
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K. K. Parhi, “Algorithm transformation techniques for concurrent processors,” Proceedings of the IEEE, Vol. 77, pp. 1879-1895, Dec. 1989.
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(1989)
Proceedings of the IEEE
, vol.77
, pp. 1879-1895
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Parhi, K.K.1
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2
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0024700229
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Pipeline interleaving and parallelism in recursive digital filters—Part I: Pipelining using scattered look-ahead and decomposition
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July
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K. K. Parhi and D. G. Messerschmitt, “Pipeline interleaving and parallelism in recursive digital filters—Part I: Pipelining using scattered look-ahead and decomposition,” IEEE Trans, on Acoustics, Speech and Signal Proc, Vol. 37, pp. 1099-1117, July 1989.
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(1989)
IEEE Trans, on Acoustics, Speech and Signal Proc
, vol.37
, pp. 1099-1117
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Parhi, K.K.1
Messerschmitt, D.G.2
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3
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0024702010
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Pipeline interleaving and parallelism in recursive digital filters—Part II: Pipelined incremental block filtering
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July
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K. K. Parhi and D. G. Messerschmitt, “Pipeline interleaving and parallelism in recursive digital filters—Part II: Pipelined incremental block filtering,” IEEE Trans. on Acoustics, Speech and Signal Proc, Vol. 27, pp. 1118-1134, July 1989.
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(1989)
IEEE Trans. on Acoustics, Speech and Signal Proc
, vol.27
, pp. 1118-1134
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Parhi, K.K.1
Messerschmitt, D.G.2
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4
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0026853681
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Low power CMOS digital design
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April
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A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low power CMOS digital design,” IEEE J. of Solid-State Circuits, Vol. 27, pp. 473-484, April 1992.
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(1992)
IEEE J. of Solid-State Circuits
, vol.27
, pp. 473-484
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Chandrakasan, A.P.1
Sheng, S.2
Brodersen, R.W.3
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5
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0016036849
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Parallel solution of recurrence problems
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March
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High speed recursive digital filter realization
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Loomis, H.H.1
Sinha, B.2
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7
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34250885644
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Concurrent architectures for two-dimensional recursive digital filtering
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June
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K. K. Parhi and D. G. Messerschmitt, “Concurrent architectures for two-dimensional recursive digital filtering,” IEEE Trans, on Circuits and Systems, Vol. 36, pp. 813-829, June 1989.
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(1989)
IEEE Trans, on Circuits and Systems
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Parhi, K.K.1
Messerschmitt, D.G.2
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8
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Parallel Viterbi decoding by breaking the compare-select feedback bottleneck
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Aug.
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Fettweis, G.1
Meyr, H.2
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10
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0026169529
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Pipelining in dynamic programming architectures
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June
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K. K. Parhi, “Pipelining in dynamic programming architectures,” IEEE Trans, on Signal Processing, Vol. 39, pp. 1442-1450, June 1991.
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(1991)
IEEE Trans, on Signal Processing
, vol.39
, pp. 1442-1450
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Parhi, K.K.1
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11
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0026186482
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Pipelining in algorithms with quantizer loops
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July
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K. K. Parhi, “Pipelining in algorithms with quantizer loops,” IEEE Trans. on Circuits and Systems, Vol. 38, pp. 745-754, July 1991.
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(1991)
IEEE Trans. on Circuits and Systems
, vol.38
, pp. 745-754
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Parhi, K.K.1
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13
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0026821944
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An 85 MHz 4th order programmable IIR digital filter chip
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Feb.
-
M. Hatamian and K. K. Parhi, “An 85 MHz 4th order programmable IIR digital filter chip,” IEEE J. of Solid-State Circuits, pp. 175-183, Feb. 1992.
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(1992)
IEEE J. of Solid-State Circuits
, pp. 175-183
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Hatamian, M.1
Parhi, K.K.2
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14
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0001484005
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Block implementation of adaptive digital filters
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June
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G. A. Clark, S. K. Mitra, and S. R. Parker, “Block implementation of adaptive digital filters,” IEEE Trans, on Acoustics, Speed and Signal Proc, vol. 29, pp. 744–752, June 1981.
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IEEE Trans, on Acoustics, Speed and Signal Proc
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Clark, G.A.1
Mitra, S.K.2
Parker, S.R.3
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15
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0022665338
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The block-processing FTF adaptive algorithm
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Feb.
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J. M. Cioffi, “The block-processing FTF adaptive algorithm,” IEEE Trans. on Acoustics, Speech and Signal Proc, Vol. 34, pp. 77-90, Feb. 1986.
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IEEE Trans. on Acoustics, Speech and Signal Proc
, vol.34
, pp. 77-90
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Cioffi, J.M.1
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16
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0142031805
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Pipelining the decision feedback equalizer
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J. M. Cioffi, P. Fortier, S. Kasturia, and G. Dudevoir, “Pipelining the decision feedback equalizer,” IEEE DSP Workshop, 1988.
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(1988)
IEEE DSP Workshop
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Cioffi, J.M.1
Fortier, P.2
Kasturia, S.3
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17
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2542512156
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High sampling rate adaptive decision feedback equalizer
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Feb.
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A. Gatherer and T.H.-Y. Meng, “High sampling rate adaptive decision feedback equalizer,” IEEE Trans. on Signal Processing, vol. 41, pp. 1000–1005, Feb. 1993.
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IEEE Trans. on Signal Processing
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Gatherer, A.1
Meng, T.H.-Y.2
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18
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0023326946
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Arbitrarily high sampling rate adaptive filters
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April
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T. Meng and D. G. Messerschmitt, “Arbitrarily high sampling rate adaptive filters,” IEEE Trans. on Acoustics, Speech and Signal Proc, Vol. 35, pp. 455-470, April 1987.
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IEEE Trans. on Acoustics, Speech and Signal Proc
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Meng, T.1
Messerschmitt, D.G.2
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19
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0344124984
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Concurrent cellular VLSI adaptive filter architectures
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Oct.
-
K. K. Parhi and D. G. Messerschmitt, “Concurrent cellular VLSI adaptive filter architectures,” IEEE Trans. on Circuits and Systems, Vol. 34, pp. 1141-1151, Oct. 1987.
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(1987)
IEEE Trans. on Circuits and Systems
, vol.34
, pp. 1141-1151
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Parhi, K.K.1
Messerschmitt, D.G.2
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20
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0024733684
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The LMS algorithm with delayed coefficient adaptation
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Sept.
-
G. Long, F. Ling, and J. G. Proakis, “The LMS algorithm with delayed coefficient adaptation,” IEEE Trans. Acoust., Speech, Signal Processing, Vol. 37, No. 9, pp. 1397-1405, Sept. 1989.
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Long, G.1
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21
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0026707001
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Corrections to “The LMS algorithm with delayed coefficient adaptation
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Jan.
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G. Long, F. Ling, and J. G. Proakis, “Corrections to “The LMS algorithm with delayed coefficient adaptation,”” IEEE Trans. Signal Processing, Vol. 40, No. 1, pp. 230-232, Jan. 1992.
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, pp. 230-232
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Long, G.1
Ling, F.2
Proakis, J.G.3
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22
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0025636881
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A modular pipelined implementation of a delayed LMS transversal adaptive filter
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New Orleans
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M. D. Meyer and D. P. Agrawal, “A modular pipelined implementation of a delayed LMS transversal adaptive filter,” Proc. 1990 IEEE Int. Symp. Circuits and Systems, New Orleans, pp. 1943-1946.
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Proc. 1990 IEEE Int. Symp. Circuits and Systems
, pp. 1943-1946
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Meyer, M.D.1
Agrawal, D.P.2
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23
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84941455509
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A pipelined LMS adaptive filter architecture
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Calif., Nov.
-
N. R. Shanbhag and K. K. Parhi, “A pipelined LMS adaptive filter architecture,” Proc. 25th \Asilomar Conf. on Sig., Sys., and Comput., Calif., Nov. 1991, pp. 668-672.
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(1991)
Proc. 25th \Asilomar Conf. on Sig., Sys., and Comput
, pp. 668-672
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Shanbhag, N.R.1
Parhi, K.K.2
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24
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0023383913
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Design alternatives for adaptive digital lattice filters and a new bit-serial architecture
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July
-
K. Konstantinides and N. Kanopoulos, “Design alternatives for adaptive digital lattice filters and a new bit-serial architecture,” IEEE Trans. Circuits and Systems, Vol. CAS-34, No. 7, July 1987.
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(1987)
IEEE Trans. Circuits and Systems
, vol.CAS-34
, Issue.7
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Konstantinides, K.1
Kanopoulos, N.2
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25
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0026274903
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A fully systolic adaptive filter implementation
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Toronto
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D. Chester, R. Young, and M. Petrowski, “A fully systolic adaptive filter implementation,” Proc. of 1991 Acous., Speech, Signal Processing, Toronto, pp. 2109-2112.
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Proc. of 1991 Acous., Speech, Signal Processing
, pp. 2109-2112
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Chester, D.1
Young, R.2
Petrowski, M.3
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27
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0027589902
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A pipelined adaptive lattice filter architecture
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May
-
N. R. Shanbhag and K. K. Parhi, “A pipelined adaptive lattice filter architecture,” IEEE Trans. on Signal Processing, Vol. 41, pp. 1925-1939, May 1993.
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(1993)
IEEE Trans. on Signal Processing
, vol.41
, pp. 1925-1939
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Shanbhag, N.R.1
Parhi, K.K.2
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28
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84946964159
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A pipelined differential vector quantizer architecture for real-time video applications
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Raleigh, NC, Sept.
-
N. R. Shanbhag and K. K. Parhi, “A pipelined differential vector quantizer architecture for real-time video applications,” in Proc IEEE Workshop on Visual Signal Processing and Communications, Raleigh, NC, Sept. 1992, pp. 9-14.
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(1992)
Proc IEEE Workshop on Visual Signal Processing and Communications
, pp. 9-14
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-
Shanbhag, N.R.1
Parhi, K.K.2
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31
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0021455219
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On supercomputing with systolic/wavefront array processors
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July
-
S.-Y. Kung, “On supercomputing with systolic/wavefront array processors,” Proceedings of the IEEE, Vol. 72, pp. 867-884, July 1984.
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(1984)
Proceedings of the IEEE
, vol.72
, pp. 867-884
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Kung, S.-Y.1
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32
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0016441291
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Adaptive linear estimation for stationary M-dependent processes
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Jan.
-
J. Kim and L. D. Davisson, “Adaptive linear estimation for stationary M-dependent processes,” IEEE Trans. Inform. Theory, Vol. IT-21, pp. 23-31, Jan. 1975.
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(1975)
IEEE Trans. Inform. Theory
, vol.IT-21
, pp. 23-31
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Kim, J.1
Davisson, L.D.2
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33
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0022053930
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Design of a DPCM codec for VLSI realization in CMOS technology
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April
-
P. Pirsch, “Design of a DPCM codec for VLSI realization in CMOS technology,” Proceedings of IEEE, Vol. 73, No. 4, pp. 592-598, April 1985.
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(1985)
Proceedings of IEEE
, vol.73
, Issue.4
, pp. 592-598
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Pirsch, P.1
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34
-
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0027211603
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Roundoff error analysis of the pipelined ADPCM coder
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Chicago, IL, May
-
N. R. Shanbhag and K. K. Parhi, “Roundoff error analysis of the pipelined ADPCM coder,” in Proc. IEEE Intl. Symp. on Circuits and Systems, Chicago, IL, May 1993, pp. 886-889.
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(1993)
Proc. IEEE Intl. Symp. on Circuits and Systems
, pp. 886-889
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Shanbhag, N.R.1
Parhi, K.K.2
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35
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85028667742
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VLSI implementation of a 100 MHz pipelined ADPCM codec chip
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Veldhoven, The Netherlands, Oct.
-
N. R. Shanbhag and K. K. Parhi, “VLSI implementation of a 100 MHz pipelined ADPCM codec chip,” in Proc. IEEE VLSI Signal Processing Workshop, Veldhoven, The Netherlands, Oct. 1993, pp. 114-122.
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(1993)
Proc. IEEE VLSI Signal Processing Workshop
, pp. 114-122
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-
Shanbhag, N.R.1
Parhi, K.K.2
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36
-
-
0026108176
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Static rate-optimal scheduling of iterative dataflow programs via optimal unfolding
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Feb.
-
K. K. Parhi and D. G. Messerschmitt, “Static rate-optimal scheduling of iterative dataflow programs via optimal unfolding,” IEEE Trans. on Comput., Vol. 40, No. 2, pp. 178–195, Feb. 1991.
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(1991)
IEEE Trans. on Comput
, vol.40
, Issue.2
, pp. 178-195
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Parhi, K.K.1
Messerschmitt, D.G.2
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37
-
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0026140187
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A systematic approach for the design of digit-serial signal processing architectures
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April
-
K. K. Parhi, “A systematic approach for the design of digit-serial signal processing architectures,” IEEE Trans. on Circuits and Systems, Vol. 38, No. 4, pp. 358-375, April 1991.
-
(1991)
IEEE Trans. on Circuits and Systems
, vol.38
, Issue.4
, pp. 358-375
-
-
Parhi, K.K.1
-
38
-
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33749922921
-
Design of pipelined lattice IIR digital filters
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Calif., Nov.
-
J.-G. Chung and K. K. Parhi, “Design of pipelined lattice IIR digital filters,” Proc. 25th Asilomar Conf. on Sig., Sys., and Comput., Calif., Nov. 1991, pp. 1021-1025.
-
(1991)
Proc. 25th Asilomar Conf. on Sig., Sys., and Comput
, pp. 1021-1025
-
-
Chung, J.-G.1
Parhi, K.K.2
-
39
-
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84947661014
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Pipelined adaptive DFE architectures
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San Diego, CA, July
-
N. R. Shanbhag and K. K. Parhi, “Pipelined adaptive DFE architectures,” in Proc. SPIE Intl. Symp. on Optics, Imaging and Inst., Adv. Algorithms, Architecture, Implementations—IV, Vol. 2027, San Diego, CA, July 1993.
-
(1993)
Proc. SPIE Intl. Symp. on Optics, Imaging and Inst., Adv. Algorithms, Architecture, Implementations—IV
, vol.2027
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Shanbhag, N.R.1
Parhi, K.K.2
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