The Latchup Risk of CMOS-Technology in Space

IEEE Transactions on Nuclear Science

Volumn 40, Issue 6, 1993, Pages 1831-1837

  Moreau, Yves ^a   De La Rochette, Hélène ^a   Bruguier, Guy ^a   Gasiot, Jean ^a   Pélanchon, Frédéric ^a   Sudre, Christophe ^a   Ecoffet, Robert ^b  

^a UNIVERSITÉ MONTPELLIER II   (France)

^b CNES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC INVERTERS; IONS; MATHEMATICAL MODELS; RADIATION HARDENING; SPACE APPLICATIONS; STATISTICAL METHODS; TECHNOLOGY; THREE DIMENSIONAL;

CAPTURE CROSS SECTION; CMOS INVERTER CELL; CMOS TECHNOLOGY; HEAVY ION STRIKE; ION ENERGY; ION TRACKS; LATCHUP RISK; RADIATION TOLERANCE;

CMOS INTEGRATED CIRCUITS;

EID: 0027840199     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.273473     Document Type: Article

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