Single Event Gate Rupture of Power DMOS Transistors

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 671-674

  Darwish, M N ^a   Shibib, M A ^a   Pinto, M R ^a   Titus, J L ^b  

^a LUCENT TECHNOLOGIES   (United States)

^b NAVAL SURFACE WARFARE CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAILURE (MECHANICAL); TRANSISTORS; GATES (TRANSISTOR); LEAKAGE CURRENTS; NUMERICAL METHODS;

FAILURE MECHANISM; POWER; SINGLE-EVENT GATE RUPTURE; SURFACE FIELD; THICK GATE OXIDES;

RADIATION HARDENING; MOS DEVICES;

GATE OXIDE; SINGLE EVENT GATE RUPTURE (SEGR); SURFACE FIELD;

EID: 0027816868     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A.E. Waskiewicz et al., IEEE Trans. Nucl. Sci., Vol. NS-33, p. 1710,1986.
2. T.A. Fisher IEEE Trans. Nucl. Sci., Vol. NS-34 (6), p.1786 1987.
3. J.Titus, et al., IEEE Trans. Nuclear Science, Vol. NS-36 (6), pp. 2375-2382 1989.
4. TF Wrobel, IEEE Trans. Nuclear Science, Vol. 34 (6), p. 1262,1987.
5. M.R. Pinto, PADRE Version 2.3 User's Manual, (AT&T) Bell Laboratories, 1992).