Threshold Voltage Controlled 0.1-μm MOSFET Utilizing Inversion Layer as Extreme Shallow Source/Drain

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 123-126

  Noda, Hiromasa ^a   Murai, Fumio ^a   Kimura, Shin'ichiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; THRESHOLD VOLTAGE; GATES (TRANSISTOR); ION IMPLANTATION; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR JUNCTIONS;

CHANNEL CHARACTERISTICS; CONVENTIONAL MOSFETS; MOSFETS; SHALLOW SOURCES; SHALLOW-JUNCTIONS; SHORT CHANNELS; SIDEWALL SPACER; SOURCE AND DRAINS; SOURCE-DRAIN; VOLTAGE-CONTROLLED;

MOSFET DEVICES;

CHANNEL CHARACTERISTICS; INVERSION LAYER; SUB GATES; THRESHOLD VOLTAGE;

EID: 0027816863     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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2. S. Kimura, H. Noda, D. Hisamoto, and E. Takeda, "A 0.1-μm elevated source and drain MOSFET fabricated by phase-shifted lithography," IEDM Tech. Dig. 950 (1991).
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8. H. Noda, K. Nakamura, and S. Kimura, "Significance of charge sharingin causing threshold voltage roll-off in highly doped 0.1-μm Si MOSFETs and its suppression by atomic layer doping (ALD)," Ext. Abs. SSDM, 23 (1993).
9. J. Tanaka, S. Kimura, H. Noda, T. Toyabe, and S. Ihara, "A Sub-0.1μm grooved gate MOSFET with high immunity to short-channel effects, in this issue.