A 0.6 µm2 256Mb Trench DRAM Cell with Self-Aligned Buried Strap (BEST)

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 627-630

  Nesbit, L ^a   Alsmeier, J ^a   Chen, B ^a   DeBrosse, J ^a   Fahey, P ^a   Gall, M ^a   Gambino, J ^a   Gernhardt, S ^a   Ishiuchi, H ^a   Kleinhenz, R ^a   Mandelman, J ^a   Mii, T ^a   Morikado, M ^a   Nitayama, A ^a   Parke, S ^a   Wong, H ^a   Bronner, G ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; INTEGRATED CIRCUIT DESIGN; CELLULAR ARRAYS; ELECTRIC CONNECTORS; ETCHING; SEMICONDUCTOR DEVICE MANUFACTURE; SUBSTRATES;

BIT LINES; BURIED STRAPS; DESIGN RULES; DRAM CELLS; SELF-ALIGNED; SIMPLE++; SMALL CELLS; TEST CHIPS; UNIQUE FEATURES;

PHOTOLITHOGRAPHY; RANDOM ACCESS STORAGE;

FOLDED BITLINE CELL; MERGED ISOLATION AND NODE TRENCH (MINT); TRENCH CELL;

EID: 0027814761     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. G. Kitsukawa et al., "256Mb DRAM technologies for file applications," 1993 IEEE International Solid-State Circuits Conference, pp. 48-49, 1993.
2. T. Sugibayashi et al, "A 30nm 256Mb DRAM with multi-divided array structure," 1993 IEEE International Solid-State Circuits Conference, pp. 50-51, 1993.
3. J.H. Ahn et al., "Micro Villus Patterning (MVP) technology For 256Mb DRAM stack cell," 1992 Symposium on VLSI Technology Digest of Technical Papers, pp. 12-13, 1992.
4. D. Kenney et al., "A buried-plate trench cell for a 64-Mb DRAM," 1992 Symposium on VLSI Technology Digest of Technical Papers, pp. 14-15, 1992.
5. K. Sunouchi et al, "Process integration for 64M DRAM using an Asymmetrical Stacked Trench capacitor (AST) Cell," 1990 Symposium on VLSI Technology Digest of Technical Papers, pp. 647-650, 1990.
6. B. Davari et al., "A variable-size Shallow Trench Isolation (STI) technology with diffused sidewall doping for submicron CMOS," 1988 IEDM Technical Digest, pp. 92-95, 1988.
7. T.V. Rajeevakumar, et al., "Trench storage capacitors for high density DRAMs," 1991 IEDM Technical Digest, pp. 835-838, 1991.