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Volumn , Issue , 1993, Pages 485-488

Compact MOS modeling for analog circuit simulation

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; CIRCUIT SIMULATION; ANALOG STORAGE; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; SIMULATION; TRANSISTORS;

EID: 0027814443     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (40)

References (11)
  • 1
    • 19244367217 scopus 로고
    • MOSFET modeling for analog circuit CAD: problems and prospects
    • Y. Tsividis and K. Suyama, "MOSFET modeling for analog circuit CAD: problems and prospects", Proc. CICC 1993, p. 14.1.1.
    • (1993) Proc. CICC , pp. 1411
    • Tsividis, Y.1    Suyama, K.2
  • 3
    • 84914939929 scopus 로고
    • The series resistance of submicron MOSFETs and its effect on their characteristics
    • F. M. Klaassen, P. T. J. Biermans and R. M. D. Velghe, "The series resistance of submicron MOSFETs and its effect on their characteristics", Proc. ESSDERC 1988, p. 257.
    • (1988) Proc. ESSDERC , pp. 257
    • Klaassen, F.M.1    Biermans, P.T.J.2    Velghe, R.M.D.3
  • 4
    • 84907818369 scopus 로고
    • Compact modelling of the MOSFET drain conductance
    • F. M. Klaassen and R. M. D. Velghe, "Compact modelling of the MOSFET drain conductance", Proc. ESSDERC 1989, p. 418.
    • (1989) Proc. ESSDERC , pp. 418
    • Klaassen, F.M.1    Velghe, R.M.D.2
  • 5
    • 84907844125 scopus 로고
    • A charge and capacitance model for modern MOSFETs
    • T. Smedes and F. M. Klaassen, "A charge and capacitance model for modern MOSFETs", Proc. ESSDERC 1990, p. 141.
    • (1990) Proc. ESSDERC , pp. 141
    • Smedes, T.1    Klaassen, F.M.2
  • 6
    • 0025575772 scopus 로고
    • Effects of lightly doped drain configuration on capacitance characteristics of sub-micron MOSFETs
    • T. Smedes and F. M. Klaassen, "Effects of lightly doped drain configuration on capacitance characteristics of sub-micron MOSFETs", IEDM Tech. Digest 1990, p. 197.
    • (1990) IEDM Tech. Digest , pp. 197
    • Smedes, T.1    Klaassen, F.M.2
  • 7
    • 0023332094 scopus 로고
    • Physical and CAD models for VLSI MOSFET
    • G. T Wright, "Physical and CAD models for VLSI MOSFET", IEEE Transactions on Electron Devices ED-34 1987, pp. 823-833.
    • (1987) IEEE Transactions on Electron Devices , vol.ED-34 , pp. 823-833
    • Wright, G.T.1
  • 8
    • 84954106097 scopus 로고
    • The impact of scaling on hot-carrier degradation and supply voltage of deep-submicron NMOS transistors
    • P. H. Woerlee et al., "The impact of scaling on hot-carrier degradation and supply voltage of deep-submicron NMOS transistors", IEDM Tech. Digest 1991, p. 537.
    • (1991) IEDM Tech. Digest , pp. 537
    • Woerlee, P.H.1
  • 10
    • 0027879116 scopus 로고
    • A high-resolution study of two-dimensional oxidation-enhanced diffusion in silicon
    • M. van Dort et al., "A high-resolution study of two-dimensional oxidation-enhanced diffusion in silicon", IEDM Tech. Digest 1993.
    • (1993) IEDM Tech. Digest
    • Van Dort, M.1
  • 11
    • 84975335011 scopus 로고
    • A low power 0.25 μm CMOS Technology
    • P. H. Woerlee et al., "A low power 0.25 μm CMOS Technology", IEDM Tech. Digest 1992, p. 31.
    • (1992) IEDM Tech. Digest , pp. 31
    • Woerlee, P.H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.