Stand-by/active mode logic for sub-2 V 1G/4Gb DRAMs

1993 Symposium on VLSI Circuits Digest of Technical Papers

Volumn , Issue , 1993, Pages 83-84

  Takashima, Daisaburo ^a   Watanabe, Sigeyoshi ^a   Sakui, Koji ^a   Nakano, Hiroaki ^a   Ohuchi, Kazunori ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

MOS DEVICES; RANDOM ACCESS STORAGE; RELIABILITY; TRANSISTORS;

DEVICE SCALING; DYNAMIC RANDOM ACCESS MEMORY (DRAM); GIGA-BIT DRAM; MOS TRANSISTOR RELIABILITY;

LOGIC DEVICES;

EID: 0027814243     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)