Selection of operation mode on SOI/MOSFET's for high-resistivity load static memory cell

IEEE International SOI Conference

Volumn , Issue , 1993, Pages 94-95

  Inoue, Y ^a   Yamaguchi, Y ^a   Yamaguchi, T ^a   Takahashi, J ^a   Iwamatsu, T ^a   Wada, T ^a   Nishimura, Y ^a   Nishimura, T ^a   Tsubouchi, N ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC FIELD EFFECTS; ELECTRIC INVERTERS; FABRICATION; FLIP FLOP CIRCUITS; RANDOM ACCESS STORAGE; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY; SIMULATORS; STABILITY; TRANSISTORS;

BACK-GATE BIAS; CIRCUIT SIMULATOR; OPERATION MODE; SILICON ON INSULATOR/MOSFET; STATIC NOISE MARGIN; STATIC RANDOM ACCESS MEMORY CELL; SUBSTRATE BIAS; THRESHOLD VOLTAGE;

MOSFET DEVICES;

EID: 0027814091     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)