SMAC: A scene matching chip

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1993, Pages 184-187

  Ranganathan, N ^a   Sastry, Raghu ^a   Venkatesan, R ^a   Yoder, Joseph W ^a   Keezer, David ^a  

^a UNIVERSITY OF SOUTH FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; HIERARCHICAL SYSTEMS; IMAGE PROCESSING; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MULTIPROCESSING SYSTEMS; VLSI CIRCUITS;

HIERARCHICAL SCENE MATCHING; SCENE MATCHING CHIP (SMAC);

MICROPROCESSOR CHIPS;

EID: 0027811663     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)