-
1
-
-
0003406298
-
Design and Validation of Computer Protocols
-
Prentice Hall. Englewood Cliffs, N.J.
-
G.J. Holzmann, Design and Validation of Computer Protocols, Prentice Hall. Englewood Cliffs, N.J., 1991.
-
(1991)
-
-
Holzmann, G.J.1
-
2
-
-
0004258810
-
Programming in Occam
-
Prentice Hall. Englewood Cliffs N.J.
-
G. Jones. Programming in Occam, Prentice Hall. Englewood Cliffs. N.J., 1987.
-
(1987)
-
-
Jones, G.1
-
3
-
-
0023544236
-
Introduction to the ISO Specification Language LOTOS
-
T. Bolognesi and E. Brinksma, “Introduction to the ISO Specification Language LOTOS,” Computer Networks and ISDN Systems. Vol. 14. No. 1. 1987, pp. 25–59.
-
(1987)
Computer Networks and ISDN Systems
, vol.14
, Issue.1
, pp. 25-59
-
-
Bolognesi, T.1
Brinksma, E.2
-
4
-
-
0002230692
-
Compiling Occam into FPGAs FPGAs
-
W. Moore and W. Luk. eds. England
-
I. Page and W. Luk. “Compiling Occam into FPGAs,” in FPGAs. W. Moore and W. Luk. eds., Abingdon EE&CS Books. Abingdon. England. 1991, pp. 271–283.
-
(1991)
Abingdon EE&CS Books. Abingdon
, pp. 271-283
-
-
Page, I.1
Luk, W.2
-
5
-
-
0003568839
-
IEEE Standard VHDL Language Reference Manual
-
IEEE.New York N.Y.
-
IEEE Standard VHDL Language Reference Manual. IEEE. New York. N.Y., 1988.
-
(1988)
-
-
-
6
-
-
5844316622
-
Electronic Design Interchange Format Version 2 0 0
-
Electronic Industries Assoc.Washington, D.C.
-
Electronic Design Interchange Format Version 2 0 0. Electronic Industries Assoc., Washington, D.C., 1989.
-
(1989)
-
-
-
7
-
-
0001531470
-
A Note on Reliable Full-Duplex Transmission over Half-Duplex Links
-
May
-
K.A. Bartlett. R.A. Scantlebury, and P.T. Wilkinson. “A Note on Reliable Full-Duplex Transmission over Half-Duplex Links,” Comm. ACM. Vol. 12, No. 5. May 1969, pp. 260–265.
-
(1969)
Comm. ACM
, vol.12
, Issue.5
, pp. 260-265
-
-
Bartlett, K.A.1
Scantlebury, R.A.2
Wilkinson, P.T.3
-
8
-
-
84901975043
-
The C++ Answer Book
-
Addison-Wesley Publishing. Reading, Mass
-
T.L. Hansen. The C++ Answer Book. Addison-Wesley Publishing. Reading, Mass., 1990.
-
(1990)
-
-
Hansen, T.L.1
-
9
-
-
84944022766
-
Empirical Evaluation of Multilevel Logic Minimization Tools for an FPGA Technology
-
W. Moore and W. Luk. eds., Abingdon EE&CS Books, AbingdonEngland
-
M. Schlag, P.K. Chan, and J. Kong, “Empirical Evaluation of Multilevel Logic Minimization Tools for an FPGA Technology,” in FPGAs. W. Moore and W. Luk. eds., Abingdon EE&CS Books, Abingdon, England, 1991, pp. 201–213.
-
(1991)
FPGAs
, pp. 201-213
-
-
Schlag, M.1
Chan, P.K.2
Kong, J.3
-
10
-
-
0026284334
-
A Formally Verified System for Logic Synthesis
-
IEEE CS Press Los Alamitos Calif., Order No. 2270
-
M. Aagaard and M. Leeser, “A Formally Verified System for Logic Synthesis,” Proc. Int'l Conf. on Computer Design, IEEE CS Press, Los Alamitos, Calif., Order No. 2270. 1991, pp. 346–350.
-
(1991)
Proc. Int'l Conf. on Computer Design
, pp. 346-350
-
-
Aagaard, M.1
Leeser, M.2
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