Effect of trench processing conditions on complementary bipolar analog devices with SOI/trench isolation

Proceedings of the 1993 Bipolar/Bicoms Circuits and Technology

Volumn , Issue , 1993, Pages 41-44

  Jerome, R ^a   Post, I ^a   Huffstater, K ^a   Wodek, G ^a   Travnicek, P ^a   Williams, D ^a  

^a United Technologies Kidde   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CORRELATION METHODS; DIELECTRIC MATERIALS; LEAKAGE CURRENTS; LINEAR NETWORKS; RAMAN SPECTROSCOPY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY; STRESSES;

COMPLEMENTARY BIPOLAR DEVICES; DIELECTRIC ISOLATION; SOI/TRENCH ISOLATION; TRENCH PROCESSING CONDITIONS;

BIPOLAR SEMICONDUCTOR DEVICES;

EID: 0027808584     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/bipol.1993.617464     Document Type: Conference Paper

References (6)