Logic optimization with multi-output gates

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1993, Pages 416-420

  Watanabe, Yosinori ^a   Guerra, Lisa ^a   Brayton, Robert K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTATIONAL METHODS; FUNCTION EVALUATION; GRAPH THEORY; HEURISTIC METHODS; LOGIC DESIGN; LOGIC GATES; MINIMIZATION OF SWITCHING NETS; OPTIMIZATION;

CONCURRENT MINIMIZATION; LOGIC OPTIMIZATION; MAXIMALLY COMPATIBLE SETS; MULTILEVEL COMBINATIONAL LOGIC CIRCUITS; MULTIPLE OUTPUT GATES; PERMISSIBLE FUNCTIONS; SINGLE OUTPUT GATE CLUSTERING;

COMBINATORIAL CIRCUITS;

EID: 0027806831     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)