ASLCScan: A scan design technique for asynchronous sequential logic circuits

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1993, Pages 159-162

  Wey, Chin Long ^a   Shieh, Ming Der ^a   Fisher, P David ^a  

^a MICHIGAN STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT OSCILLATIONS; ELECTRIC FAULT CURRENTS; ELECTRIC NETWORK SYNTHESIS; GRAPH THEORY; LOGIC DESIGN; MATHEMATICAL MODELS; REDUNDANCY;

HUFFMAN MODEL; SIGNAL TRANSITION GRAPH (STG); SINGLE STUCK AT FAULT MODEL;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 0027804405     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)