Graph-based Simplex algorithm for minimizing the layout size and the delay on timing critical paths

Volumn , Issue , 1993, Pages 703-708

  Wang, Lih Yang ^a   Lai, Yen Tai ^a   Liu, Bin Da ^a   Chang, Ting Chung ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; CRITICAL PATH ANALYSIS; ELECTRIC NETWORK SYNTHESIS; GRAPH THEORY; LINEAR PROGRAMMING; MINIMIZATION OF SWITCHING NETS; OPTIMIZATION; VLSI CIRCUITS;

CRITICAL PATH DELAY; GRAPH BASED SIMPLEX ALGORITHMS; LAYOUT COMPACTION PROBLEM; LAYOUT SIZE; TIMING CRITICAL PATHS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0027795511     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)