Topological design of clock distribution network based on non-zero clock skew specifications

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 1993, Pages 468-471

  Neves, Jose Luis ^a   Friedman, Eby G ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CRITICAL PATH ANALYSIS; ELECTRIC CLOCKS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; POLES AND ZEROS; SIGNAL PROCESSING; TREES (MATHEMATICS);

CLOCK DISTRIBUTION NETWORK; CLOCK SKEW SPECIFICATIONS; OPTIMAL CLOCK PATH DELAY; SEQUENTIALLY ADJACENT REGISTERS;

ELECTRIC NETWORK TOPOLOGY;

EID: 0027721264     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)