A Discussion on the Temperature Dependence of Latch-Up Trigger Current in CMOS/BiCMOS Structures

IEEE Transactions on Electron Devices

Volumn 40, Issue 11, 1993, Pages 2023-2028

  Aoki, Takahiro ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC NETWORK PARAMETERS; ELECTRIC RESISTANCE; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LUMPED PARAMETER NETWORKS; SEMICONDUCTOR DEVICE STRUCTURES; THERMAL EFFECTS;

CMOS/BICMOS STRUCTURES; LATCH UP TRIGGER CURRENT; TEMPERATURE DEPENDENCE;

FLIP FLOP CIRCUITS;

EID: 0027702156     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.239744     Document Type: Article

References (7)

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3. A. G. Lewis “Latchup suppression in fine-dimension shallow p-well CMOS circuits,” IEEE Trans. Electron Devices, vol. ED-21, pp. 1472–1481, 1984.
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5. F. S. Shoucair “High-temperature latchup characteristics in VLSI CMOS circuits,” IEEE Trans. Electron Devices, vol. ED-35, pp. 2424–2426, 1988.
6. R. B. Brown, K. Wu, M. Ghezzo, D. M. Brown, E. Downey, and D. Hanchar “Junction-isolated CMOS for high-temperature microelectronics,” IEEE Trans. Electron Devices, vol. ED-36, pp. 1854–1856, 1989.
7. P. Norton and J. Brandt “Temperature coefficient of resistance for p- and n-type silicon,” Solid-State Electron., vol. 21, pp. 969–974, 1978.