Threaded prefetching: An adaptive instruction prefetch mechanism

Microprocessing and Microprogramming

Volumn 39, Issue 1, 1993, Pages 1-15

  Baeg Kim, Seong ^a   Soon Park, Myung ^a   Park, Sun Ho ^a   Lyul Min, Sang ^a   Shin, Heonshik ^a   Sang Kim, Chong ^a   Jeong, Deog Kyoon ^a  

^a Seoul National University   (South Korea)

Author keywords

instruction cache; Prefetching; trace driven simulation

Indexed keywords

CONTROL SYSTEMS;

ADAPTIVE INSTRUCTION PREFETCH SCHEME; INSTRUCTION BLOCKS; PROCESSOR INSTRUCTION BLOCK; THREADED PREFETCHING; TRACE-DRIVEN SIMULATION;

MICROPROCESSOR CHIPS;

EID: 0027695233     PISSN: 01656074     EISSN: None     Source Type: Journal    
DOI: 10.1016/0165-6074(93)90257-L     Document Type: Article

References (13)

1. Cache performance of the SPEC benchmark suite
2. Aspects of cache memory and instruction buffer performance
3. Achieving high instruction cache performance with an optimizing compiler
4. Improving directed-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
5. Branch prediction strategies and branch target buffer design
6. Program optimization for instruction caches
7. The effect of context switches on cache performance
8. Profile guided code positioning
9. The performance impact of block sizes and fetch strategies
10. Sequential program prefetching in memory hierarchies
11. Cache memories
12. A study of branch prediction strategies
13. Tracing with pixie