A 1.5-ns 32-b CMOS ALU in Double Pass-Transistor Logic

IEEE Journal of Solid-State Circuits

Volumn 28, Issue 11, 1993, Pages 1145-1151

  Makoto, Suzuki ^a   Norio, Ohkubo ^a   Shinbo, Toshinobu ^a   Toshiaki, Yamanaka ^a   Shimizu, Akihiro ^a   Sasaki, Katsuro ^b   Nakagome, Yoshinobu ^a  

^a HITACHI LTD   (Japan)

^b HITACHI AMERICA LTD   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CAPACITANCE; CARRY LOGIC; CMOS INTEGRATED CIRCUITS; ELECTRIC PROPERTIES; LOGIC DESIGN; LOGIC GATES; MICROPROCESSOR CHIPS; MOS DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE;

ARITHMETIC LOGIC UNIT; CARRY PROPAGATION PATH; CMOS ALU; CONDITIONAL CARRY SELECTION; DOUBLE PASS TRANSISTOR LOGIC; GATE SPEED; SERIES CONNECTED PASS TRANSISTORS;

TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

EID: 0027694895     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.245595     Document Type: Article

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