An IC Chip of Chua’s Circuit

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 40, Issue 10, 1993, Pages 614-625

  Cruz, Jose M ^a   Chua, Leon O ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHAOS THEORY; CMOS INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; ELECTRIC BATTERIES; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; MONOLITHIC INTEGRATED CIRCUITS; NEURAL NETWORKS; POTENTIOMETERS (RESISTORS); SYNCHRONIZATION; VLSI CIRCUITS;

CELLULAR NEURAL NETWORK; CHAOS SYNCHRONIZATION; CHAOTIC SIGNAL; CHUA'S CIRCUIT; LINEAR RESISTOR; LINEAR STORAGE ELEMENT; MICROELECTRONIC CHIP;

MICROPROCESSOR CHIPS;

EID: 0027685297     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.246162     Document Type: Article

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