A programmable image processing system using FPGAs

International Journal of Electronics

Volumn 75, Issue 4, 1993, Pages 725-730

  Chan, S C ^a   Ngai, H O ^b   Ho, K L ^b  

^a CITY UNIVERSITY OF HONG KONG   (Hong Kong)

^b UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; COMPUTER ARCHITECTURE; DATA COMMUNICATION SYSTEMS; DIGITAL SIGNAL PROCESSING; MULTIPROCESSING PROGRAMS; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; REAL TIME SYSTEMS; SIGNAL FILTERING AND PREDICTION;

BIT LEVEL SYSTOLIC CONCEPT; FIELD PROGRAMMABLE GATE ARRAY (FPGA); PROGRAMMABLE IMAGE PROCESSING SYSTEM; PROGRAMMABLE IMAGE PROCESSING SYSTEM (PIPS); THROUGHPUT RATE;

IMAGE PROCESSING;

EID: 0027683976     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/00207219308907150     Document Type: Article

References (5)

1. Gokhale, M., Holmes, W., Kopser, A., Lucas, S., and Minnich, R., 1991, Building and using a highly parallel programmable logic array. I.E.E.E. Computer, (January), pp. 81-89. .
2. Kung, S. Y., 1988, YLSI Array Processors (Englewood CliiTs, NJ: Prentice Hall).
3. OflaZer, K., 1983, Design and implementation of a single chip l-D median filter. I.E.E.E.Transactions on Acoustics, Speech and Signal Processing, 31, 1164-1168.
4. Richards, D. S., 1990, VLSI median filters. I.E.E.E. Transactions on Acoustics, Speech and Signal Processing, 38, 145-153.
5. Wu, C. W., 1991, Bit-level pipelined 2-D digital filters for real-time image processing. I.E.E.E. Transactions on Circuits and Systems for Video Technology,1, 22-34.