A Multiprocessor Architecture for Viterbi Decoders with Linear Speedup

IEEE Transactions on Signal Processing

Volumn 41, Issue 9, 1993, Pages 2907-2917

  Feygin, Gennady ^a   Gulak, Patrick G ^a   Chow, Paul ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DECODING; MULTIPROCESSING SYSTEMS; VLSI CIRCUITS;

VITERBI DECODERS;

DIGITAL SIGNAL PROCESSING;

EID: 0027665962     PISSN: 1053587X     EISSN: 19410476     Source Type: Journal    
DOI: 10.1109/78.236512     Document Type: Article

References (19)

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