A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2m)

IEEE Transactions on Computers

Volumn 42, Issue 9, 1993, Pages 1141-1146

  Wang, Chin Liang ^a   Lin, Jung Lung ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

design; Finite field division; finite field inversion; logic circuit; serial in serial out; standard basis; system of linear equations; systolic array; VLSI

Indexed keywords

ALGORITHMS; COMPUTER CIRCUITS; ERROR ANALYSIS; ERROR CORRECTION; INFORMATION THEORY; INVERSE PROBLEMS; LINEAR ALGEBRA; LINEARIZATION; LOGIC CIRCUITS; VLSI CIRCUITS;

FINITE FIELD DIVISION; FINITE FIELD INVERSION; SYSTOLIC ARCHITECTURE;

LOGIC DESIGN;

EID: 0027663290     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.241603     Document Type: Article

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