Binary Partition Algorithms and VLSI Architectures for Median and Rank Order Filtering

IEEE Transactions on Signal Processing

Volumn 41, Issue 9, 1993, Pages 2937-2942

  Lee, Charng Long ^a   Jen, Chein Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; SIGNAL FILTERING AND PREDICTION; VLSI CIRCUITS;

BINARY PARTITION ALGORITHMS; RANK ORDER FILTERING;

DIGITAL SIGNAL PROCESSING;

EID: 0027659422     PISSN: 1053587X     EISSN: 19410476     Source Type: Journal    
DOI: 10.1109/78.236516     Document Type: Article

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