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Volumn 1, Issue 3, 1993, Pages 356-364

Parallel-Concurrent Fault Simulation

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER APPLICATIONS; COMPUTER SIMULATION; ELECTRIC FAULT LOCATION; EQUIVALENT CIRCUITS; LOGIC CIRCUITS; LOGIC DESIGN; MATHEMATICAL MODELS;

EID: 0027658725     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.238447     Document Type: Article
Times cited : (8)

References (18)
  • 2
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    • Parallel fault simulation using distributed processing
    • Dec
    • Y. M. Levendel, P. R. Menon, and S. H. Patel, “Parallel fault simulation using distributed processing,” Bell Syst. Tech. J vol. 62, no. 10, pp. 3107–3130, Dec. 1983.
    • (1983) Bell Syst. Tech. J , vol.62 , Issue.10 , pp. 3107-3130
    • Levendel, Y.M.1    Menon, P.R.2    Patel, S.H.3
  • 3
    • 0021481531 scopus 로고
    • A survey of hardware accelerators used in computer aided design
    • Aug
    • T. Blank, “A survey of hardware accelerators used in computer aided design,” IEEE Design & Test Comput., Aug. 1984.
    • (1984) IEEE Design & Test Comput
    • Blank, T.1
  • 5
    • 84937349719 scopus 로고
    • Digital logic simulation in a time-based, table-driven environment: part 2. parallel fault simulation
    • Mar
    • E. W. Thompson and S. A. Szygenda, “Digital logic simulation in a time-based, table-driven environment: part 2. parallel fault simulation,” Comput., vol. 8, pp. 38–49, Mar. 1975.
    • (1975) Comput , vol.8 , pp. 38-49
    • Thompson, E.W.1    Szygenda, S.A.2
  • 6
    • 84938738286 scopus 로고
    • A deductive method for simulating faults in logic circuits
    • May
    • D. B. Armstrong, “A deductive method for simulating faults in logic circuits,” IEEE Trans. Comput., vol. C-21, pp. 464–471, May 1972.
    • (1972) IEEE Trans. Comput , vol.C-21 , pp. 464-471
    • Armstrong, D.B.1
  • 8
    • 8444236225 scopus 로고
    • Fault simulation with the parallel valued list algorithm
    • Dec
    • S. Kyushik, “Fault simulation with the parallel valued list algorithm,” VLSI Syst. Design, pp. 36–43, Dec. 1985.
    • (1985) VLSI Syst. Design , pp. 36-43
    • Kyushik, S.1
  • 9
    • 0020921615 scopus 로고
    • Fault simulation using parallel valued lists
    • (Santa Clara, CA)
    • P. R. Moorby, “Fault simulation using parallel valued lists,” in Proc. IEEE lnt. Conf. Computer-Aided Design (Santa Clara, CA), 1983, pp. 101–102.
    • (1983) Proc. IEEE lnt. Conf. Computer-Aided Design , pp. 101-102
    • Moorby, P.R.1
  • 10
    • 0024942420 scopus 로고
    • Differential fault simulation-A fast method using minimal memory
    • June
    • W.-T. Cheng and M.-L. Yu, “Differential fault simulation—A fast method using minimal memory,” in Proc. Design Automation Conf, June 1989, pp. 424–428.
    • (1989) Proc. Design Automation Conf , pp. 424-428
    • Cheng, W.-T.1    Yu, M.-L.2
  • 11
    • 0026819183 scopus 로고
    • PROOFS: A fast memory-efficient sequential circuit fault simulator
    • Feb
    • T. M. Niermann, W.-T. Cheng, and J. H. Patel, “PROOFS: A fast memory-efficient sequential circuit fault simulator,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 198–207, Feb. 1992.
    • (1992) IEEE Trans. Computer-Aided Design , vol.11 , pp. 198-207
    • Niermann, T.M.1    Cheng, W.-T.2    Patel, J.H.3
  • 12
    • 0020946267 scopus 로고
    • Fault modeling and logic simulation of MOS VLSI circuits based on logic expression extraction
    • lnt. Conf. Computer-Aided Design (Santa Clara, CA), Sept
    • I. N. Hajj and D. G. Saab, “Fault modeling and logic simulation of MOS VLSI circuits based on logic expression extraction,” in Proc. IEEE lnt. Conf. Computer-Aided Design (Santa Clara, CA), Sept. 1983, pp. 99–100.
    • (1983) Proc. IEEE , pp. 99-100
    • Hajj, I.N.1    Saab, D.G.2
  • 13
    • 33747020799 scopus 로고
    • The diagnosis of asynchronous sequential switching systems
    • S. Seshu and D. N. Freeman, “The diagnosis of asynchronous sequential switching systems,” IRE Trans. Electron. Computing, vol. EC-11, pp. 459–465, 1962.
    • (1962) IRE Trans. Electron. Computing , vol.EC-11 , pp. 459-465
    • Seshu, S.1    Freeman, D.N.2
  • 14
    • 0019636496 scopus 로고
    • Fault-simulation methods-extensions and comparison
    • Nov
    • Y. H. Levendel and P. R. Menon, “Fault-simulation methods—extensions and comparison,” Bell Syst. Tech. J., vol. 60, pp. 2235–2259, Nov. 1981.
    • (1981) Bell Syst. Tech. J , vol.60 , pp. 2235-2259
    • Levendel, Y.H.1    Menon, P.R.2
  • 15
    • 0142046626 scopus 로고
    • Concurrent simulation of nearly identical digital networks
    • Apr
    • E. G. Ulrich and T. Baker, “Concurrent simulation of nearly identical digital networks,” Comput., vol. 7, pp. 39–44, Apr. 1974.
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    • Ulrich, E.G.1    Baker, T.2
  • 17
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    • Symbolic logic simulation of MOS circuits
    • I. N. Hajj and D. G. Saab, “Symbolic logic simulation of MOS circuits,” in Proc. Int. Symp. Circuits Syst., 1983, pp. 246–249.
    • (1983) Proc. Int. Symp. Circuits Syst , pp. 246-249
    • Hajj, I.N.1    Saab, D.G.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.