Motion estimation architecture for video compression

IEEE Transactions on Consumer Electronics

Volumn 39, Issue 3, 1993, Pages 292-297

  Chan, Eric ^a   Panchanathan, Sethuraman ^a  

^a UNIVERSITY OF OTTAWA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ERROR ANALYSIS; ESTIMATION; VELOCITY MEASUREMENT; VLSI CIRCUITS;

BROADBAND NETWORKS; INTERBLOCK DEPENDENCY; MOTION ESTIMATION; VIDEO COMPRESSION;

VIDEO SIGNAL PROCESSING;

EID: 0027649146     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/30.234596     Document Type: Article

References (7)

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3. L. D. Vos and M. Stegherr, “Parameterizable VLSI Architecture for the Full-Search Block Matching Algorithm”, IEEE trans. on Circuits and Systems, Vol. 36, No. 10, pp. 1309–1316, 1989.
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