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Volumn 40, Issue 8, 1993, Pages 1563-1565

A 64-GHzfrand 3.6-V BVCE0Si Bipolar Transistor Using in situ Phosphorus-Doped and Large-Grained Polysilicon Emitter Contacts

Author keywords

[No Author keywords available]

Indexed keywords

DOPING (ADDITIVES); ELECTRIC VARIABLES MEASUREMENT; PHOSPHORUS; SILICON;

EID: 0027649107     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.223725     Document Type: Article
Times cited : (8)

References (12)
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  • 2
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  • 3
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    • 63-75 GHzfrSiGe-base heterojunction bipolar technology
    • G. L. Patton et al., “63-75 GHzf r SiGe-base heterojunction bipolar technology,” in Symp. VLSI Technol., 1990, pp. 49–50.
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    • Patton, G.L.1
  • 4
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    • A 20 ps/G Si bipolar IC using advanced SST with collector ion implantation
    • S. Konaka et al., “A 20 ps/G Si bipolar IC using advanced SST with collector ion implantation,” in Extended Abstracts SSDM, 1987, pp. 331–334.
    • (1987) Extended Abstracts SSDM , pp. 331-334
    • Konaka, S.1
  • 5
    • 0025659616 scopus 로고
    • Perimeter and plug effects in deep submicron polysilicon emitter bipolar transistors
    • J. N. Burghartz et al., “Perimeter and plug effects in deep submicron polysilicon emitter bipolar transistors,” in Symp. VLSI Technol., 1990, pp. 55–56.
    • (1990) Symp. VLSI Technol , pp. 55-56
    • Burghartz, J.N.1
  • 6
    • 84954089943 scopus 로고
    • A 64 GHz Si bipolar transistor using in-situ phosphorus doped polysilicon emitter technology
    • M. Nanba et al., “A 64 GHz Si bipolar transistor using in-situ phosphorus doped polysilicon emitter technology,” in IEDM Tech. Dig., 1991, pp. 443–446.
    • (1991) IEDM Tech. Dig , pp. 443-446
    • Nanba, M.1
  • 7
    • 84941465201 scopus 로고
    • Advanced device process technology of 0.3 −m self-aligned bipolar LSIs
    • Y. Tamaki et al., “Advanced device process technology of 0.3 μm self-aligned bipolar LSIs,” in BCTM Tech. Dig., 1990, pp. 70–73.
    • (1990) BCTM Tech. Dig , pp. 70-73
    • Tamaki, Y.1
  • 8
    • 0026400173 scopus 로고
    • An ultra-high emitter efficiency transistor with a low-temperature processed polysilicon emitter for high-speed bipolar ULSIs
    • M. Kondo et al., “An ultra-high emitter efficiency transistor with a low-temperature processed polysilicon emitter for high-speed bipolar ULSIs,” in Symp. VLSI Techol., 1991, pp. 64–65.
    • (1991) Symp. VLSI Techol , pp. 64-65
    • Kondo, M.1
  • 9
    • 0025503463 scopus 로고
    • Tself-aligned silicon bipolar transistors with ion-implanted base profiles
    • J. Wamock et al., “50-GHz f T self-aligned silicon bipolar transistors with ion-implanted base profiles,” IEEE Electron Device Lett., vol. 11, pp. 475–477, 1990.
    • (1990) IEEE Electron Device Lett. , vol.11 , pp. 475-477
    • Wamock, J.1
  • 10
    • 0018545806 scopus 로고
    • The SIS tunnel emitter: A theory for emitter with thin interface layers
    • H. C. de Graaff et al., “The SIS tunnel emitter: A theory for emitter with thin interface layers,” IEEE Trans. Electron Devices, vol. ED-26, pp. 1771–1776, 1979.
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  • 12
    • 0019080362 scopus 로고
    • Effect of emitter contact on current gain of silicon bipolar devices
    • T. H. Ning et al., “Effect of emitter contact on current gain of silicon bipolar devices,” IEEE Trans. Electron Devices, vol. ED-27, pp. 2051–2055, 1980.
    • (1980) IEEE Trans. Electron Devices , vol.ED-27 , pp. 2051-2055
    • Ning, T.H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.