A Practical High-Latchup Immunity Design Methodology for Internal Circuits in the Standard Cell-Based CMQS/BiCMOS LSI’s

IEEE Transactions on Electron Devices

Volumn 40, Issue 8, 1993, Pages 1432-1436

  Aoki, Takahiro ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LSI CIRCUITS;

CIRCUIT IMMUNITY DESIGN; HIGH DENSITY INTERVAL CIRCUITS; SHUNT RESISTANCE; TRIGGER CURRENT;

CMOS INTEGRATED CIRCUITS;

EID: 0027647341     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.223702     Document Type: Article

References (6)

1. D. B. Estreich, “The physics and modeling of latch-up and CMOS integrated circuits,” Stanford Electron. Labs. Tech. Rep. G-201-9, 1980.
2. T. Aoki, R. Kasai, and S. Horiguchi, “Transient characteristics in bulk CMOS structures,” Electron. Lett., vol. 19, no. 19, pp. 758–759, 1983.
3. R. D. Rung, H. Momose, and Y. Nagakubo, “Deep trench isolated CMOS devices,” in 1EDM Tech. Dig., 1982, pp. 237–240.
4. R. R. Troutman, “Epitaxial layer enhancement of n-well guard rings for CMOS circuit,” IEEE Electron Device Lett., vol. EDL-4, pp. 438–440, 1982.
5. Y. Niitsu, G. Sasaki, H. Nihira, and K. Kanzaki, “Resistance modulation effect in n-well CMOS,” IEEE Trans. Electron Devices, vol. ED-32, no. 11, pp. 2227–2231, 1985.
6. R, R. Troutman and H. P. Zappe, “A transient analysis of latch-up in bulk CMOS,” IEEE Trans. Electron Devices, vol. ED-30, no. 2, pp. 170–179, 1983.