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Volumn 42, Issue 8, 1993, Pages 962-967

On the Lower Bound to the VLSI Complexity of Number Conversion from Weighted to Residue Representation

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; DATA STRUCTURES; EQUIVALENCE CLASSES; NUMBER THEORY; OPTIMAL SYSTEMS; TABLE LOOKUP; VLSI CIRCUITS;

EID: 0027646103     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.238486     Document Type: Article
Times cited : (5)

References (11)
  • 1
    • 0024104042 scopus 로고
    • Efficient VLSI networks for converting an integer from binary to residue numbers and vice versa
    • R. M. Capocelli and R. Giancarlo, “Efficient VLSI networks for converting an integer from binary to residue numbers and vice versa,” IEEE Trans. Circuits Syst., vol. CAS-35, no. 11, pp. 1425–1430, 1988.
    • (1988) IEEE Trans. Circuits Syst , vol.CAS-35 , Issue.11 , pp. 1425-1430
    • Capocelli, R.M.1    Giancarlo, R.2
  • 2
    • 0042757293 scopus 로고
    • A VLSI structure for x(modm) operation
    • G. Alia and E. Martinelli, “A VLSI structure for x(modm) operation,” J. VLSI Signal Processing, vol. 1, pp. 257–264, 1990.
    • (1990) J. VLSI Signal Processing , vol.1 , pp. 257-264
    • Alia, G.1    Martinelli, E.2
  • 3
    • 0025503332 scopus 로고
    • VLSI binary-residue converters for pipelined processing
    • G. Alia and E. Martinelli, “VLSI binary-residue converters for pipelined processing,” Comput. J., vol. 33, no. 5, pp. 473-475, 1990.
    • (1990) Comput. J , vol.33 , Issue.5 , pp. 473-475
    • Alia, G.1    Martinelli, E.2
  • 4
    • 0004217544 scopus 로고
    • A complexity theory for VLSI
    • Dept. of Comput. Science, Carnegie-Mellon University, Rept. CMU-CS-80-140
    • C. D. Thompson, “A complexity theory for VLSI,” Ph.D. dissertation, Dept. of Comput. Science, Carnegie-Mellon University, Rept. CMU-CS-80-140, 1980.
    • (1980) Ph.D. dissertation
    • Thompson, C.D.1
  • 7
    • 52449147995 scopus 로고
    • Area-time lower-bound techniques with applications to sorting
    • G. Bilardi and F. P. Preparata, “Area-time lower-bound techniques with applications to sorting,” Algorithmica, vol. 1, 1986.
    • (1986) Algorithmica , vol.1
    • Bilardi, G.1    Preparata, F.P.2
  • 8
    • 0021446827 scopus 로고
    • AT2-optimal VLSI integer division and integer square rooting
    • K. Mehlhom, “AT 2-optimal VLSI integer division and integer square rooting,” Integration, vol. 2, pp. 163–167, 1984.
    • (1984) Integration , vol.2 , pp. 163-167
    • Mehlhom, K.1
  • 9
    • 0020780067 scopus 로고
    • Area-time optimal VLSI integer multiplier with minimum computation time
    • K. Mehlhorn and F. P. Preparata, “Area-time optimal VLSI integer multiplier with minimum computation time,” Inform. Contr., vol. 58, pp. 137–156, 1983.
    • (1983) Inform. Contr , vol.58 , pp. 137-156
    • Mehlhorn, K.1    Preparata, F.P.2
  • 10
    • 0026188738 scopus 로고
    • A VLSI modulo m multiplier
    • G. Alia and E. Martinelli, “A VLSI modulo m multiplier,” IEEE Trans. Comput., vol. C-40, no. 7, pp. 873–878, 1991.
    • (1991) IEEE Trans. Comput , vol.C-40 , Issue.7 , pp. 873-878
    • Alia, G.1    Martinelli, E.2
  • 11
    • 0020102009 scopus 로고
    • A regular layout for parallel adders
    • R. P. Brent and H. T. Kung, “A regular layout for parallel adders,” IEEE Trans. Comput., vol. C-31, no. 3, pp. 260–264, 1982.
    • (1982) IEEE Trans. Comput , vol.C-31 , Issue.3 , pp. 260-264
    • Brent, R.P.1    Kung, H.T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.