Simulation of Sub-0.1-μm MOSFET's with Completely Suppressed Short-Channel Effect

IEEE Electron Device Letters

Volumn 14, Issue 8, 1993, Pages 396-399

  Tanaka, Junko ^a   Toyabe, Toru ^a   Ihara, Sigeo ^a   Kimura, Shin'ichiro ^a   Noda, Hiromasa ^a   Itoh, Kiyoo ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION;

CADDETH-NP DEVICE SIMULATOR; GATE INSULATOR; GROOVED-GATE MOSFET; SUPPRESSED SHORT-CHANNEL EFFECT; THRESHOLD VOLTAGE LOWERING;

MOSFET DEVICES;

EID: 0027640656     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.225591     Document Type: Article

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