Paralleled Hardware Annealing for Optimal Solutions on Electronic Neural Networks

IEEE Transactions on Neural Networks

Volumn 4, Issue 4, 1993, Pages 588-599

  Lee, Bang W ^a   Sheu, Bing J ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE STORAGE; COMPUTER SIMULATION; COMPUTER SOFTWARE; ITERATIVE METHODS; OPTIMAL SYSTEMS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PATTERN RECOGNITION; PROBABILITY; TRANSFER FUNCTIONS;

BACK PROPAGATION NETWORKS; ELECTRONIC NEURAL NETWORKS; HOPFIELD DATA CONVERSION NETWORKS; ITERATIVE NETWORKS; OPTIMAL SOLUTION; PARALLELED HARDWARE ANNEALING; SELF ORGANIZING NETWORKS; SIMULATED ANNEALING; TRANSIENT RESPONSE;

NEURAL NETWORKS;

EID: 0027629411     PISSN: 10459227     EISSN: 19410093     Source Type: Journal    
DOI: 10.1109/72.238314     Document Type: Article

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