Application of a Floating Well Concept to a latchup-Free, Low-Cost, Smart Power High-Side Switch Technology

IEEE Transactions on Electron Devices

Volumn 40, Issue 7, 1993, Pages 1340-1342

  Bafleur, M ^a   Buxo, J ^a   Puig Vidal, M ^a   Givelin, P ^b   Macary, V ^b   Sarrabayrouse, G ^c  

^a Laboratoire d'Automatique et d'Analyse des Systèmes du CNRS Universitat de Barcelona ^*  (France)

^b MOTOROLA INC   (United States)

^c Laboratoire d'Automatique et d'Analyse des Systèmes du CNRS ^*  (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC CIRCUITS; MOS DEVICES; TRANSISTORS;

COST EFFECTIVE TECHNOLOGY; FLOATING WELL CONCEPT; TRANSIENT VOLTAGES;

SEMICONDUCTOR SWITCHES;

EID: 0027628053     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.216442     Document Type: Article

References (3)

1. R.D. Rung and H. Momose, “DC holding and dynamic triggering characteristics of bulk CMOS latchup,” IEEE Trans. Electron Devices, vol. ED-30, no. 12, pp. 1647–1655, Dec. 1983.
2. E. Thibodeaux, “Getting the most of CMOS devices for analog switching jobs,” Electronics, pp. 69–74, Dec. 25, 1975.
3. A. Elmoznine, J. Buxo, M. Bafleur, and P. Rossel, “The smart power high-side switch: Description of a specific technology, its basic devices and monitoring circuitries,” IEEE Trans. Electron Devices, vol. 37, no. 4, pp. 1154–1161, Apr. 1990.