Statistical Timing Analysis of Combinational Logic Circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 1, Issue 2, 1993, Pages 126-137

  Jyu, Horng Fei ^a   Malik, Sharad ^a   Devadas, Srinivas ^b   Keutzer, Kurt W ^c  

^a PRINCETON UNIVERSITY   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^c SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CIRCUITS; TIMING CIRCUITS;

BENCHMARK CIRCUITS; CIRCUIT DESIGN; DELAY ANALYSIS; FALSE PATHS;

VLSI CIRCUITS;

EID: 0027614893     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.238423     Document Type: Article

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