Optimization of Cyclic Redundancy-Check Codes with 24 and 32 Parity Bits

IEEE Transactions on Communications

Volumn 41, Issue 6, 1993, Pages 883-892

  Castagnoli, Guy ^a   Bräuer, Stefan ^b   Herrmann, Martin ^c  

^a Staefa Control System AG ^*  (Switzerland)

^b Reliability Laboratory ETH Zentrum ^*  (Switzerland)

^c ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR DETECTION; MATHEMATICAL MODELS; OPTIMIZATION; SIGNAL ENCODING;

BINARY SYMMETRIC CHANNELS; BLOCK LENGTH; CYCLIC REDUNDANCY CHECK CODES; PARITY BITS;

DATA COMMUNICATION SYSTEMS;

EID: 0027612155     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/26.231911     Document Type: Article

References (0)