VLSI Architectures for Discrete Wavelet Transforms

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 1, Issue 2, 1993, Pages 191-202

  Parhi, Keshab K ^a   Nishitani, Takao ^b  

^a UNIVERSITY OF MINNESOTA   (United States)

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DESIGN; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

DILATION EQUATIONS; SCALING; WAVELET TRANSFORMS;

COMPUTER ARCHITECTURE;

EID: 0027612122     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.238416     Document Type: Article

References (17)

1. S.G. Mallat, “A theory for multiresolution signal decomposition: The wavelet representation,” IEEE Trans. Patt. Anal. Mach. Intell. , vol. 11, pp. 674–693, July 1989.
2. S.G. Mallat, “Multifrequency channel decompositions of images and wavelet models,” IEEE Trans. Acoust., Speech, Signal Processing, vol. 37, pp. 2091–2110, Dec. 1989.
3. I. Daubechies, “Orthonormal bases of compactly supported wavelets,” Commun. Pure Appl. Math., vol. 41, no. 7, pp. 909–996, 1988.
4. G. Strang, “Wavelets and dilation equations: A brief introduction,” SIAM Rev., vol. 31, no. 4, pp. 614–627, Dec. 1989.
5. O. Rioul, and M. Vetterli, “Wavelets and signal processing,” IEEE Signal Processing Mag., pp. 14–38, Oct. 1991.
6. M. Ohta, M. Yano, and T. Nishitani, “Entropy coding for wavelet transform of image and its applications for motion picture coding,” in Proc. SPIE Visual Communications and Image Processing: Visual Communications, vol. 160, Boston, MA, pp. 456–466, Nov. 1991.
7. O. Rioul, and P. Duhamel, “Fast algorithms for discrete and continuous wavelet transforms,” IEEE Trans. Inform. Theory, vol 38, pp. 569–586, Mar. 1992.
8. K.K. Parhi C.Y. Wang, and A.P. Brown, “Synthesis of control circuits in folded pipelined DSP architectures,” IEEE J. Solid-State Circuits, vol. 27, pp. 29–43, Jan. 1992.
9. G. Knowles, “VLSI architecture for the discrete wavelet transform,” Electron. Lett., vol. 26, no. 15, pp. 1184–1185, July 1990.
10. K.K. Parhi, “Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation,” IEEE Trans. Circuits Syst-II, vol 39, pp. 423–440, July 1992.
11. “Video data format converters using minimum number of registers,” IEEE Trans. Circuits Syst. Video Technol., vol. 2, pp. 255–267, June 1992.
12. K.K. Parhi and T. Nishitani, “Folded VLSI architectures for discrete wavelet transforms,” in Proc. IEEE Int. Symp. on Circuits and Systems, Chicago, IL, pp. 1734–1737, May 1993.
13. K.K. Parhi, “A systematic approach for design of digit-serial signal processing architectures,” IEEE Trans. Circuits Syst., vol. 38, pp. 358–375, Apr. 1991.
14. R.I. Hartley and P.F. Corbett, “Digit-serial processing techniques,” IEEE Trans. Circuits Syst., vol. 37, pp. 707–719, June 1990.
15. S.G. Smith and P.B. Denyer, Serial Data Computation, Boston: Kluwer Academic Press, 1988
16. A.P. Chandrakasan, S. Sheng, and R.W. Brodersen, “Low-power CMOS digital design,” IEEE J. Solid-State Circuits, vol. 27, pp. 473–484, Apr. 1992.
17. T. Miyazaki, “A study on a two-dimensional wavelet transform structure for a video codec,” in Proc. 1992 Nat. Conv. of IEICE of Japan, pp. 7–49, Mar. 1992 (in Japanese).