Circuit Simulation by Hierarchical Waveform Relaxation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 12, Issue 6, 1993, Pages 845-860

  Saviz, Peter ^a   Wing, Omar ^b  

^a INTEL CORPORATION   (United States)

^b Department of Electrical Engineering Columbia University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CONVERGENCE OF NUMERICAL METHODS; ELECTRIC NETWORK TOPOLOGY; HIERARCHICAL SYSTEMS; ITERATIVE METHODS; MATHEMATICAL MODELS; RELAXATION PROCESSES; VLSI CIRCUITS; WAVEFORM ANALYSIS;

CIRCUIT SIMULATION; CIRCUIT SIMULATION PROGRAM PYRAMID; HIERARCHICAL WAVEFORM RELAXATION METHOD; REPARTITIONING; SENSITIVITY BASED SUBCIRCUIT MERGING;

ELECTRIC NETWORK ANALYSIS;

EID: 0027609757     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.229760     Document Type: Article

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