A Neural Network Approach to Topological Via-Minimization Problems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 12, Issue 6, 1993, Pages 770-779

  Funabiki, Nobuo ^a   Takefuji, Yoshiyasu ^b  

^a Sumitomo Metal Industries   (Japan)

^b CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MINIMIZATION OF SWITCHING NETS; NEURAL NETWORKS; VLSI CIRCUITS;

CONSTRAINED VIA MINIMIZATION PROBLEMS; TOPOLOGICAL VIA MINIMIZATION PROBLEMS;

ELECTRIC NETWORK TOPOLOGY;

EID: 0027608556     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.229751     Document Type: Article

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