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Volumn 12, Issue 5, 1993, Pages 672-683

Stepwise Equivalent Conductance Circuit Simulation Technique

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; EQUIVALENT CIRCUITS; FIELD EFFECT TRANSISTORS; ITERATIVE METHODS; MOS DEVICES; NONLINEAR NETWORK SYNTHESIS;

EID: 0027591978     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.277612     Document Type: Article
Times cited : (14)

References (18)
  • 1
    • 0027094419 scopus 로고
    • SWEC: A step wise equivalent conductance timing simulator for CMOS VLSI circuits
    • Feb.
    • Shen Lin, M. Marek-Sadowska, and Ernest Kuh, “SWEC: A step wise equivalent conductance timing simulator for CMOS VLSI circuits,” in Proc. EDAC, pp. 142–148, Feb. 1991.
    • (1991) Proc. EDAC , pp. 142-148
    • Lin, S.1    Marek-Sadowska, M.2    Kuh, E.3
  • 5
    • 0024936340 scopus 로고
    • The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation
    • Dec.
    • R. A. Saleh and A. R. Newton, “The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 1286–1298, Dec. 1989.
    • (1989) IEEE Trans. Computer-Aided Design , vol.8 , pp. 1286-1298
    • Saleh, R.A.1    Newton, A.R.2
  • 6
    • 0020781156 scopus 로고
    • The waveform relaxation method for the time-domain analysis of large scale integrated circuits
    • July
    • E. Lelarasmee and A. E. Ruehli and A. Sangiovanni-Vincentelli, “The waveform relaxation method for the time-domain analysis of large scale integrated circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-1, pp. 131–145, July 1982.
    • (1982) IEEE Trans. Computer-Aided Design , vol.CAD-1 , pp. 131-145
    • Lelarasmee, E.1    Ruehli, A.E.2    Sangiovanni-Vincentelli, A.3
  • 10
    • 0024889661 scopus 로고
    • Event-EMU: An event-driven timing simulator for MOS VLSI circuit
    • B. D. Ackland and R. Clark, “Event-EMU: An event-driven timing simulator for MOS VLSI circuit,” in IEEE Proc. ICCAD, pp. 80–83, 1989.
    • (1989) IEEE Proc. ICCAD , pp. 80-83
    • Ackland, B.D.1    Clark, R.2
  • 11
    • 0000682349 scopus 로고
    • A switch-level timing verifier for digital MOS VLSI
    • July
    • J. K. Ousterhout, “A switch-level timing verifier for digital MOS VLSI,” IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 336–349, July 1985.
    • (1985) IEEE Trans. Computer-Aided Design , vol.CAD-4 , pp. 336-349
    • Ousterhout, J.K.1
  • 13
    • 0026976137 scopus 로고
    • Transient simulation of lossy interconnect
    • June
    • Shen Lin and Ernest Kuh, “Transient simulation of lossy interconnect,” in Proc. 29th Design Automation Conf., pp. 81–86, June 1992.
    • (1992) Proc. 29th Design Automation Conf. , pp. 81-86
    • Lin, S.1    Kuh, E.2
  • 14
    • 0026944320 scopus 로고
    • Transient simulation of lossy interconnects based on the recursive convolution formulation
    • Nov.
    • “Transient simulation of lossy interconnects based on the recursive convolution formulation,” IEEE Trans. Circuits Syst., vol. 39, Nov. 1992.
    • (1992) IEEE Trans. Circuits Syst. , vol.39
  • 15
    • 0021563150 scopus 로고
    • Wave convergence algorithms for the waveform relaxation method
    • Nov.
    • P. Debefve, H. Y. Hsieh, and A. E. Ruehli, “Wave convergence algorithms for the waveform relaxation method,” in IEEE Proc. ICCAD, pp. 33–35, Nov. 1984.
    • (1984) IEEE Proc. ICCAD , pp. 33-35
    • Debefve, P.1    Hsieh, H.Y.2    Ruehli, A.E.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.