A Pipelined Adaptive Lattice Filter Architecture

IEEE Transactions on Signal Processing

Volumn 41, Issue 5, 1993, Pages 1925-1939

  Shanbhag, Naresh R ^a   Parhi, Keshab K ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SYSTEMS; ALGORITHMS; COMPUTER ARCHITECTURE; CONVERGENCE OF NUMERICAL METHODS; ELECTRIC FILTERS; IMAGE COMPRESSION; PIPELINE PROCESSING SYSTEMS; VIDEO SIGNAL PROCESSING;

ADAPTIVE FILTERS; LATTICE FILTERS; PIPELINED FILTERS; SEQUENTIAL FILTERS; VIDEO COMPRESSION;

SIGNAL FILTERING AND PREDICTION;

EID: 0027589902     PISSN: 1053587X     EISSN: 19410476     Source Type: Journal    
DOI: 10.1109/78.215309     Document Type: Article

References (19)

1. K. K. Parhi, “Algorithm transformation techniques for concurrent processors,” Proc. IEEE, vol. 77, pp. 1879–1895, Dec. 1989.
2. K. K. Parhi and D. G. Messerschmitt, “Pipeline interleaving and parallelism in recursive digital filters—Part I: Pipelining using scattered look-ahead and decomposition,” IEEE Trans. Acoust., Speech, Signal Processing, vol. 37, pp. 1099–1117, July 1989.
3. K. K. Parhi and D. G. Messerschmitt, “Pipeline interleaving and parallelism in recursive digital filters—Part II: Pipelined incremental block filtering,” IEEE Trans. Acoust., Speech, Signal Processing, vol. 37, pp. 1118–1134, July 1989.
4. K. K. Parhi, “Pipelining in dynamic programming architectures,” IEEE Trans. Signal Processing, vol. 39, pp. 1442–1450, June 1991.
5. K. K. Parhi, “Pipelining in algorithms with quantizer loops,” IEEE Trans. Circuits Syst., vol. 38, pp. 745–754, July 1991.
6. K. K. Parhi, “High-speed VLSI architectures for Huffman and Viterbi decoders,” IEEE Trans. Circuits Syst. II: Analog and Digital Signal Processing, vol. 39, pp. 385–391, June 1992.
7. H.-D. Lin and D. G. Messerschmitt, “Finite state machine has unlimited concurrency,” IEEE Trans. Circuits Syst., vol. 38, pp. 465–475, May 1991.
8. K. K. Parhi and D. G. Messerschmitt, “Concurrent cellular VLSI adaptive filter architectures,” IEEE Trans. Circuits Syst., vol. 34, pp. 1141–1151, Oct. 1987.
9. T. Meng and D. G. Messerschmitt, “Arbitrarily high sampling rate adaptive filters,” IEEE Trans. Acoust., Speech, Signal Processing, vol. 35, pp. 455–470, Apr. 1987.
10. N. R. Shanbhag and K. K. Parhi, “A pipelined LMS adaptive filter architecture,” in Proc. 25th Asilomar Conf. Signals, Syst., Comput., Pacific Grove, CA, Nov. 1991, pp. 668–672.
11. M. L. Honig and D. G. Messerschmitt, Adaptive Filters: Structures, Algorithms, and Applications. Boston: Kluwer, 1984.
12. N. R. Shanbhag and K. K. Parhi, “A pipelined adaptive lattice filter architecture: Theory and applications,” in Proc. EUSIPCO ‘ 92, Brussels, Belgium, Aug. 1992.
13. N. R. Shanbhag and K. K. Parhi, “A high-speed architecture for ADPCM coder and decoder,” in Proc. 1992 IEEE Int. Symp. Circuits Syst., San Diego, CA, pp. 1499–1502.
14. G. A. Clark, S. K. Mitra, and S. R. Parker, “Block implementation of adaptive digital filters,” IEEE Trans. Acoust., Speech, Signal Processing, vol. 29, pp. 744–752, June 1981.
15. S. Theodoridis, “Pipeline architecture for block adaptive LS FIR filtering and prediction,” IEEE Trans. Acoust., Speech, Signal Processing, vol. 38, pp. 81–90, Jan. 1990.
16. J. M. Cioffi, P. Fortier, S. Kasturia, and G. Dudevoir, “Pipelining the decision feedback equalizer,” presented at the IEEE DSP Workshop, 1988.
17. A. Gatherer and T. H.-Y. Meng, “High sampling rate adaptive decision feedback equalizer,” in Proc. IEEE ICASSP ’ 90, pp. 909–912.
18. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low power CMOS digital design,” IEEE J. Solid-State Circuits, vol. 27, pp. 473–484, Apr. 1992.
19. J.-G. Chung and K. K. Parhi, “Design of pipelined lattice HR digital filters,” in Proc. 25th Asilomar Conf. Signals, Syst., Comput., Pacific Grove, CA, Nov. 1991, pp. 1021–1025.