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Volumn 28, Issue 4, 1993, Pages 510-512

Low-Power 1/2 Frequency Dividers Using 0.1 -μm CMOS Circuits Built with Ultrathin SIMOX Substrates

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ION IMPLANTATION; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES;

EID: 0027579531     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.210036     Document Type: Article
Times cited : (28)

References (9)
  • 1
    • 33746189368 scopus 로고
    • 0.1 -μm-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer
    • Y. Omura, S. Nakashima, K. Izumi, and T. Ishii, “0.1 -μm-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer,” in IEDM Tech. Dig., 1991, pp. 675–678.
    • (1991) IEDM Tech. Dig. , pp. 675-678
    • Omura, Y.1    Nakashima, S.2    Izumi, K.3    Ishii, T.4
  • 2
    • 0026103786 scopus 로고
    • Subfemtojoule deep submicrometer-gate CMOS built in ultra thin Si film on SIMOX substrates
    • Feb.
    • H. Miki et al., “Subfemtojoule deep submicrometer-gate CMOS built in ultra thin Si film on SIMOX substrates,” IEEE Trans. Electron Devices, vol. 38, no. 2, pp. 373–377, Feb. 1991.
    • (1991) IEEE Trans. Electron Devices , vol.38 , Issue.2 , pp. 373-377
    • Miki, H.1
  • 3
    • 0024870507 scopus 로고
    • Ultra-high speed CMOS circuits in thin SIMOX films
    • A. Kamgar et al., “Ultra-high speed CMOS circuits in thin SIMOX films,” in IEDM Tech. Dig., 1989, pp. 829–832.
    • (1989) IEDM Tech. Dig. , pp. 829-832
    • Kamgar, A.1
  • 4
    • 0025491670 scopus 로고
    • Practical reduction of dislocation density in SIMOX wafers
    • S. Nakashima and K. Izumi, “Practical reduction of dislocation density in SIMOX wafers,” Electron Lett., vol. 26, no. 20, pp. 1647–1649, 1990.
    • (1990) Electron Lett. , vol.26 , Issue.20 , pp. 1647-1649
    • Nakashima, S.1    Izumi, K.2
  • 6
    • 84941436455 scopus 로고
    • Technology trends in ASIC
    • Jan.
    • N. Ieda, “Technology trends in ASIC,” IEICE Trans., vol. E 74, no. 1, pp. 148–156, Jan. 1991.
    • (1991) IEICE Trans. , vol.E 74 , Issue.1 , pp. 148-156
    • Ieda, N.1
  • 7
    • 5844388763 scopus 로고
    • Process-optimization for sub-30ps BiCMOS technologies for mixed ECL/CMOS applications
    • H. Klose et al., “Process-optimization for sub-30ps BiCMOS technologies for mixed ECL/CMOS applications,” in IEDM Tech. Dig., 1991, pp. 89–92.
    • (1991) IEDM Tech. Dig. , pp. 89-92
    • Klose, H.1
  • 8
    • 84954125489 scopus 로고
    • Advanced IC fabrication technology using reliable, small-size, and high speed AlGaAs/GaAs HBT
    • T. Nittono et al., “Advanced IC fabrication technology using reliable, small-size, and high speed AlGaAs/GaAs HBT,” in IEDM Tech. Dig., 1991, pp. 931–934.
    • (1991) IEDM Tech. Dig. , pp. 931-934
    • Nittono, T.1
  • 9
    • 84954186458 scopus 로고
    • InAlAs/InGaAs double heterojunction bipolar transistors with a collector launcher structure for high speed ECL applications
    • H. Yamada et al., “InAlAs/InGaAs double heterojunction bipolar transistors with a collector launcher structure for high speed ECL applications,” in IEDM Tech. Dig., 1991, pp. 964–966.
    • (1991) IEDM Tech. Dig. , pp. 964-966
    • Yamada, H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.