A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture

IEEE Journal of Solid-State Circuits

Volumn 28, Issue 4, 1993, Pages 523-527

  Kobayashi, Tsuguo ^a   Nogami, Kazutaka ^a   Shirotori, Tsukasa ^a   Fujimoto, Yukihiro ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BUFFER CIRCUITS; COMPUTER ARCHITECTURE; RANDOM ACCESS STORAGE; SWITCHING CIRCUITS; VLSI CIRCUITS;

HIGH-SPEED SRAM; LATCH SENSE AMPLIFIERS; POWER-SAVING BUFFERS; SRAM;

DATA STORAGE EQUIPMENT;

EID: 0027576335     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.210039     Document Type: Article

References (7)

1. R. Badeau et al., “A 100MHz macropipelined CISC CMOS microprocessor,” in ISSCC Dig. Tech. Papers, Feb. 1992, pp. 106–107.
2. D. Dobberpuhl et al., “A 200MHz 64b dual-issue CMOS microprocessor,” in ISSCC Dig. Tech. Papers, Feb. 1992, pp. 107–108.
3. F. Abu-Nofal et al., “A three-million transistor microprocessor,” in ISSCC Dig. Tech. Papers. Feb. 1992, pp. 109–110.
4. 386 lM SL Microprocessor SuperSet Data Book, Intel Corp., Santa Clara, CA, Oct. 1990.
5. T. Kobayashi et al., “A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operation,” IEEE J. Solid-State Circuits, vol. 26, pp. 1586–1592, Nov. 1991.
6. O. Minato et al., “A 20ns 64K CMOS SRAM,” in ISSCC Dig. Tech. Papers, Feb. 1984, pp. 222–223.
7. M. Matsui et al., “Two novel power-down circuits on the 1Mb SRAM,” in Proc. Symp. VLSI Circ. (Tokyo), Aug. 1988, p. 55–56.