A Coupled Study by Floating-Gate and Charge-Pumping Techniques of Hot-Carrier-Induced Defects in Submicrometer ldd NMOSfet'S

IEEE Transactions on Electron Devices

Volumn 40, Issue 4, 1993, Pages 773-781

  Vuillaume, Dominique ^a   Bravaix, Alain ^a   Marchetaux, Jean Claude ^b   Boudou, Alain ^b   Lippens, Pierre Emmanuel ^a  

^a Institut Superieur de l'Electronique et du Numerique   (France)

^b BULL SA 78340 Les Clayes sous Bois ^*  (France)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; GATES (TRANSISTOR); SEMICONDUCTING SILICON; STRESSES;

CHARGE PUMPING; FLOATING GATES;

MOSFET DEVICES;

EID: 0027574665     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.202790     Document Type: Article

References (29)

1. J.S. Brugler and P.G. Jespers, “Charge pumping in MOS devices,” IEEE Trans. Electron Devices, vol. ED-16, p. 297, 1969.
2. G. Groseneken, H.E. Maes, N. Beltran, and R.F. DeKeersmaecker, “A reliable approach to charge pumping measurements in MOS transistors,” IEEE Trans. Electron Devices, vol. ED-31, p. 42, 1984.
3. P. Heremans, J. Witters, G. Groeseneken, and H.E. Maes, “Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation,” IEEE Trans. Electron Devices, vol. 36, p. 1318, 1989.
4. E. Takeda, A. Shimizu, and T. Hagiwara, “Role of hot hole injection in hot carrier effect and the small degraded channel region in MOSFET's,” IEEE Electron Device Lett., vol. EDL-4, p. 329, 1983.
5. T. Poorter and Z. Zoestbergen, “Hot carrier effects in MOS transistors,” in IEDM Tech. Dig., 1984, p. 100.
6. P. Heremans, R. Bellens, G. Groeseneken, and H.E. Maes, “Consistent model for the hot carrier degradation in n-channel and p-chan-nel MOSFET's,” IEEE Trans. Electron Devices, vol. 35, p. 2194, 1988.
7. T. Tsuchiya, T. Kobayashi, and S. Nakajima, “Hot-carrier injected oxide region and hot-electron trapping as the main cause in Si nMOSFET degradation,” IEEE Trans. Electron Devices, vol. ED-34, p. 386, 1987.
8. B.S. Doyle, M. Bourcerie, C. Bergonzoni, R. Benecchi, A. Bravaix, K.R. Mistry, and A. Boudou, “The generation and characterization of electron and hole traps created by hole injection during low gate voltage hot-carrier stressing of NMOS transistors,” IEEE Trans. Electron Devices, vol. 37, p. 1869, 1990.
9. B.S. Doyle, M. Bourcerie, J.C. Marchetaux, and A. Boudou, “The voltage dependence of degradation in NMOS transistors,” in Proc. ESSDERC Conf., 1987, p. 155.
10. E. Sangiorgi, M.R. Pinto, F. Venturi, and W. Fichtner, “A hot-carrier analysis of submicrometer MOSFET's,” IEEE Electron Device Lett., vol. 9, p. 13, 1988.
11. B.S. Doyle, M. Bourcerie, J.C. Marchetaux, and A. Boudou, “Interface state creation and charge trapping in the medium-to-high gate voltage range (Vd/2 - Vg - Vd) during hot-carrier stressing of NMOS transistors,” IEEE Trans. Electron Devices, vol. 37, p. 744, 1990.
12. A. Acovic, M. Dutoit, and M. Ilegems, “Characterization of hot-electron-stressed MOSFET's by low-temperature measurements of the drain tunnel current,” IEEE Trans. Electron Devices, vol. 37, p. 1467, 1990.
13. F.H. Gaensslen and J.M. Aitken, “Sensitive technique for measuring small MOS gate currents,” IEEE Electron Device Lett., vol. EDL-1, p. 231, 1980.
14. N.S. Saks, P.L. Heremans, L. Van Den Hove, H.E. Maes, R.F. DeKeersmaecker, and G.J. Declerk, “Observation of hot hole injection in NMOS transistors using a modified floating-gate technique,” IEEE Trans. Electron Devices, vol. ED-33, p. 1529, 1986.
15. J.C. Marchetaux, M. Bourcerie, A. Boudou, and D. Vuillaume, “Application of the floating-gate technique to the study of the NMOSFET gate current evolution due to hot-carrier aging,” IEEE Electron Device Lett., vol. 11, p. 406, 1990.
16. D. Vuillaume and B.S. Doyle, “Properties of hot carrier induced traps in MOSFET's characterized by the floating gate technique,” Solid State Electron., vol. 35, p. 1099, 1992.
17. S. Tarn, P.K. Ko, and C. Hu, “Lucky electron model of channel hot-electron injection in MOSFET's,” IEEE Trans. Electron Devices, vol. ED-31, p. 1116, 1984.
18. P. Robiin, A. Samman, and S. Bibyk, “Simulation of hot-electron trapping and aging of NMOSFET's,” IEEE Trans. Electron Devices, vol. 35, p. 2229, 1988.
19. J.C. Marchetaux, unpublished results.
20. D. Vuillaume, J.C. Marchetaux, and A. Boudou, “Evidence of acceptor-like oxide defects created by hot-carrier injection in NMOSFET's: A charge pumping study,” IEEE Electron Device Lett., vol. 12, p. 60, 1991.
21. K.R. Hofmann, C. Werner, W. Weber, and G. Dorda, “Hot electron and hole emission effects in short n-channel MOSFET's,” IEEE Trans. Electron Devices, vol. ED-32, p. 691, 1985.
22. S. Baba, A. Kita, and J. Ueda, “Mechanism of hot-carrier induced degradation in MOSFET's,” in IEDM Tech. Dig., 1986, p. 734.
23. M. Garrigues, A. Alexandre, P. Rojo, T. Pedron, K. Belhaddad, and A. Poncet, “Two-dimentional computer simulation of hot-carrier degradation in NMOSFET's,” in Proc. ESSDERC Conf., 1988, p. C4–673.
24. Y. Chen and T. Tang, “Numerical simulation of avalanche hot-carrier injection in short-channel MOSFET's,” IEEE Trans. Electron Devices, vol. 35, p. 2180, 1988.
25. M. Orlowski, C. Mazuré, A. Lill, H.M. Mühlhoff, W. Hänsch, A.V. Schwerin, and F. Neppl, “Advanced simulation for reliability optimization of submicron LDD MOSFET's,” in Proc. ESSDERC 89, 1989, p. 711.
26. J. Hui, F.C. Hsu, and J. Moll, “A new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices,” IEEE Electron Device Lett., vol. EDL-6, p. 135, 1985.
27. D. Collard and K. Taniguchi, “IMPACT–A point defect-based two dimentional process simulator: modeling the lateral oxidation-enhanced diffusion of dopants in silicon,” IEEE Trans. Electron Devices, vol. ED-33, p. 1454, 1986.
28. D. Collard, B. Baccus, E. Dubois, and D. Morel, “An integrated 2D process/device simulator for MOS technology,” in Softeware Tools for Process, Device and Circuit Modelling (Lecture notes of the short course of the Software Forum in association with the Nesiode VI Conf.) W. Crans, Ed. Dublin, Ireland: Boole Press, 1989, pp. 16–31.
29. A. Hiroki, S. Odanaka, K. Ohe, and H. Esaki, “A mobility model for submicrometer MOSFET simulations including hot-carrier-induced device degradation,” IEEE Trans. Electron Devices, vol. 35, p. 1487, 1988.