A Comparison of CVD Stacked Gate Oxide and Thermal Gate Oxide for 0.5-μm Transistors Subjected to Process-Induced Damage

IEEE Transactions on Electron Devices

Volumn 40, Issue 3, 1993, Pages 613-618

  Tseng, Hsing Huang ^a   Tobin, Philip J ^a   Hayden, James D ^a   Chang, Ko Min ^a   Miller, James W ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; CHEMICAL VAPOR DEPOSITION; DIELECTRIC PROPERTIES; HOT CARRIERS; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS;

GATE OXIDES; STACKED GATE DIELECTRICS; STACKED GATE OXIDES; THRESHOLD VOLTWGE SCATTER;

FIELD EFFECT TRANSISTORS;

EID: 0027557793     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.199368     Document Type: Article

References (6)

1. L. D. Yau, “Composite oxide gate dielectric,” presented at SRC High Reliability Gate Dielectric Topical Research Conf., Albuquerque, NM, sec. III-2, 1990.
2. G. H. Kawamoto, G. Y. Magyar, and L. D. Yau, “Hot-electron trapping in thin LPCVD SiO 2 dielectrics,” IEEE Trans. Electron Devices, vol. HD-34, p. 2450, 1987.
3. P. K. Roy, R. H. Doklan, E. P. Martin, S. F. Shive, and A. K. Sinha, “Synthesis and characterization of high quality ultrathin gate oxides for VLSI/ULSI circuits,” in IEDM Tech. Dig., 1988, p. 714.
4. P. K. Roy and A. K. Sinha, “Synthesis of high-quality ultra-thin gate oxides for ULSI applications,” AT…T Tech. J., p. 155, Nov./Dec. 1988.
5. R. Moazzami and C. Hu, “A high quality stacked thermal/LPCVD gate oxide for ULSI,” in Proc. Int. Symp. on VLSI Technology, System, and Applications (Taipei, Taiwan, ROC), 1991, p. 52.
6. J. D. Hayden et al., “A high-performance sub-half micron CMOS technology for fast SRAMs,” in IEDM Tech. Dig., 1989, p. 417.