A 180-MHz 0.8-μm BiCMOS modular memory family of DRAM and multiport SRAM

IEEE Journal of Solid-State Circuits

Volumn 28, Issue 3, 1993, Pages 222-232

  Silburt, Allan L ^a   Gibson, G F Randall ^a   Wood, Steven W ^a   Bluschke, Armin G ^a   Fujimoto, James S ^a   Kornachuk, Stephen P ^a   Nadeau Dostie, Benoit ^a   Phillips, Richard S ^b   Verma, Rajesh K ^c   Diedrich, Peter M J ^d  

^a NORTEL NETWORKS   (Canada)

^b Bayview Technologies Inc ^*  (Canada)

^c ATI Technologies ^*  (Canada)

^d MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; DIGITAL INTEGRATED CIRCUITS; DIGITAL STORAGE; HYBRID INTEGRATED CIRCUITS; MICROELECTRONICS;

ASIC DESIGN; BICMOS CIRCUITS; DIGITAL IC DESIGN; DRAMS; MEMORY CHIPS; SRAMS; SUBMICRON DEVICES;

RANDOM ACCESS STORAGE;

EID: 0027553564     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.209988     Document Type: Article

References (15)

1. R. Hadaway et al., “A sub-micron BiCMOS technology for telecommunications,” in Proc. European Solid-State Device Res. Conf. (Montreux), 1991, pp. 513–516.
2. T. Dao and F. Sevejda, “A dual-port SRAM compiler for 0.8-μm 100K BiCMOS gate arrays,” in Proc. IEEE Custom Integrated Circuits Conf., 1991, pp. 22.4.1–3.
3. H. Hana and S. Hussain, “High speed multi-port static RAM silicon compiler,” in Proc. IEEE Custom Integrated Circuits Conf, 1989, pp. 23.6.1–4.
4. H. Shinohara et al., “A flexible multi-port RAM compiler for datapath,” in Proc. IEEE Custom Integrated Circuits Conf, 1990, pp. 16.5.1–4.
5. J. Tou et al., “A submicrometer CMOS embedded SRAM compiler,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 417–424, Mar. 1992.
6. S. Shinagawa et al., “A multi-speed digital cross-connect switching VLSI using new circuit techniques in dual port RAM's,” in Proc. IEEE Custom Integrated Circuits Conf., 1991, pp. 3.4.1—4.
7. C. Ohno, “Self-timed RAM: STRAM,” Fujitsu Sci. Tech. J., vol. 24, no. 4, pp. 293–300, Dec. 1988.
8. D. Lee and R. Katz, “Using cache mechanisms to exploit nonrefreshing DRAM's for on-chip memories,” IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 657–661, Apr. 1991.
9. B. Nadeau-Dostie et al., “Serial interfacing for embedded memory testing,” IEEE Design Test Comput., pp. 52–63, Apr. 1990.
10. T. Akioka et al., “A 6-ns 256-kb BiCMOS TTL SRAM,” IEEE J. Solid-State Circuits, vol. 26, no. 3, pp. 439–443, Mar. 1991.
11. M. Takada et al., “A 5-ns 1Mb ECL BiCMOS SRAM,” IEEE J. Solid-State Circuits, vol. 25, no. 5, pp. 1057–1062, Oct. 1990.
12. E. B. Eichelberger and T. W. Williams, “A logic design structure for LSI testability,” in Proc. 14th Design Automation Conf, June 1977, pp. 462–468.
13. S. Kirkpatrick, “Modeling diffusion and collection of charge from ionizing radiation in silicon devices,” IEEE Trans. Electron Devices, vol. ED-26, no. 11, pp. 1742–1753, Nov. 1979.
14. C. M. Hsieh et al., “A field-funneling effect on the collection of alpha-particle-generated carriers in silicon devices,” IEEE Electron Device Lett., vol. EDL-2, no. 4, pp. 103–105, Apr. 1981.
15. S. Fu et al., “Alpha-particle-induced charge collection measurements and the effectiveness of a novel p-well protection barrier on VLSI memories,” IEEE Trans. Electron Devices, vol. ED-32, no. 1, pp. 49–54, Jan. 1985.