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Journal of Electronic Testing

Volumn 4, Issue 1, 1993, Pages 11-17

An approach to sequential circuit diagnosis based on formal verification techniques

(5) Cabodi, G a Camurati, P a Corno, F a Prinetto, P a Reorda, M Sonza a

a POLITECNICO DI TORINO (Italy)

Author keywords

Binary decision diagrams; diagnosis; formal verification; FSM's; symbolic state space traversal techniques

Indexed keywords

COMBINATORIAL CIRCUITS; EQUIVALENCE CLASSES; FINITE AUTOMATA; STATE SPACE METHODS; TREES (MATHEMATICS);

BINARY DECISION DIAGRAMS; DIAGNOSTIC TREE; FORMAL VERIFICATION; SEQUENTIAL CIRCUIT DIAGNOSIS;

SEQUENTIAL CIRCUITS;

EID: 0027542373 PISSN: 09238174 EISSN: 15730727 Source Type: Journal
DOI: 10.1007/BF00971936 Document Type: Article

Times cited : (3)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.