Layout Reconstruction of Complex Silicon Chips

IEEE Journal of Solid-State Circuits

Volumn 28, Issue 2, 1993, Pages 138-145

  de Riu, Ugo ^b   Fraboni, Beatrice ^a   Lall, Sanjay ^a   Ahmed, Haroon ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^b Direzione Olivetti Ricerca ^*  (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; MICROPROCESSOR CHIPS; SEMICONDUCTING SILICON; VLSI CIRCUITS;

CMOS GATE ARRAYS; COMPLEX VLSI CIRCUITS; LAYOUT RECONSTRUCTION; SEMIAUTOMATED LAYOUT; VLSI MICROPROCESSOR CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0027542367     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.192045     Document Type: Article

References (6)

1. H. J. Leamy, “Charge collection scanning electron microscopy,” J. Appl. Phys., vol. 53, no. 6, R51-R80, June 1982.
2. D. B. Holt, SEM Microcharacterisation of Semiconductors. New York: Academic, 1989.
3. J. D. Schick, Scanning Elec. Microsc., vol. I, p. 55, 1985.
4. E. I. Cole et al., “A novel method for depth profiling of semiconductor devices using capacitive voltage contrast,” J. Appl. Phys., vol. 62, no. 12, pp. 4909–4915, Dec. 1987.
5. S. M. Sze, VLSI Technology. New York: McGraw-Hill, 1988.
6. D. E. Newbury et al., Advanced Scanning Electron Microscopy and X-ray Microanalysis. New York: Plenum, 1986.