A Layout-Driven Yield Predictor and Fault Generator for VLSI

IEEE Transactions on Semiconductor Manufacturing

Volumn 6, Issue 1, 1993, Pages 77-82

  Dalal, Alexander R ^a   Franzon, Paul D ^b   Lorenzetti, Michael J ^c  

^a Microsystems Computer Corporation ^*  (United States)

^b NORTH CAROLINA STATE UNIVERSITY   (United States)

^c MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; CRYSTAL DEFECTS; ELECTRIC FAULT LOCATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; MONTE CARLO METHODS; PROBABILITY;

FAULT GENERATOR; LAYOUT DRIVEN YIELD PREDICTOR;

VLSI CIRCUITS;

EID: 0027541117     PISSN: 08946507     EISSN: 15582345     Source Type: Journal    
DOI: 10.1109/66.210661     Document Type: Article

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