SCOPUS 정보 검색 플랫폼

Journal of VLSI Signal Processing

Volumn 5, Issue 1, 1993, Pages 85-94

Generalized trace-back techniques for survivor memory management in the Viterbi algorithm

(2) Cypher, Robert a Shung, C Bernard b

a IBM ALMADEN RESEARCH CENTER (United States)

b NATIONAL CHIAO TUNG UNIVERSITY (Taiwan)

Author keywords

survivor memory; trace back; Viterbi algorithm; VLSI area requirements

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); DATA PROCESSING; DECODING; DYNAMIC PROGRAMMING; GRAPH THEORY; MANAGEMENT; RANDOM ACCESS STORAGE; STATE ASSIGNMENT; VLSI CIRCUITS;

SURVIVOR MEMORY MANAGEMENT; TRACE BACK TECHNIQUES; TRELLIS DIAGRAM; VITERBI ALGORITHM; VLSI AREA REQUIREMENTS;

DATA STORAGE EQUIPMENT;

EID: 0027264338 PISSN: 09225773 EISSN: 1573109X Source Type: Journal
DOI: 10.1007/BF01880274 Document Type: Article

Times cited : (27)

References (10)

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2
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3
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4
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- The Viterbi algorithm
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5
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7
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- Memory management in a Viterbi decoder
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- Rader, C.M.¹

8
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- O. Collins and F. Pollara, “Memory management in traceback Viterbi decoders,” TDA Progress Report 42–99, Jet Propulsion Laboratory, 1988.

9
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- G. Feygin, P.G. Gulak, and F. Pollara, “Survivor sequence memory management in Viterbi decoders,”Proc. 3rd Workshop on ECC, San Jose, CA, 1989, pp. 72–90.

10
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- CD. Thompson, “A complexity theory for VLSI,” Ph.D. thesis, Dept. of Comp. Sci., Carnegie Mellon University, 1980.

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.